CY2410
MPEG Clock Generator with VCXO
Features
Benefits
■
Integrated phase-locked loop (PLL)
■
Highest-performance PLL tailored for multimedia applications
■
Low-jitter, high-accuracy outputs
■
Meets critical timing requirements in complex system designs
■
VCXO with analog adjust
■
Large ±150-ppm range, better linearity
■
3.3V operation
■
Application compatibility for a wide variety of designs
■
Compatible with MK3727 (–1, –5)
■
Enables design compatibility
■
Advanced Features
■
Matches nonlinear MK3727A VCXO control curve (-5)
■
Digital VCXO control
■
Electromagnetic interference (EMI) reduction for standards
compliance
■
Second source for existing designs
Part
Number
Outputs
Output
Frequencies
Input Frequency Range
VCXO Control
Curve
Other Features
CY2410–1
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz linear
Compatible with MK3727
CY2410–5
1
13.5-MHz pullable crystal input per
Cypress specification
1 copy of 27 MHz nonlinear
Matches MK3727A nonlinear
VCXO Control Curve
CY2410-1, -5 Logic Block Diagram
13.5 XIN
OSC
OUTPUT
DIVIDERS
Φ
Q
XOUT
VCO
27 MHz
P
VCXO
PLL
VDD
Cypress Semiconductor Corporation
Document #: 38-07317 Rev. *E
•
198 Champion Court
VSS
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 22, 2008
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CY2410
CY2410-3 Logic Block Diagram
13.5 XIN
OSC
Q
OUTPUT
DIVIDERS
Φ
XOUT
VCO
27 MHz
P
PLL
SCLK
SDAT
Digital VCXO
Serial
Programming
Interface
VDD
VSS
Pin Configuration
Figure 1. CY2410-1, CY2401-5 8-Pin SOIC
XIN
1
8
XOUT
VDD
VCXO
2
7
NC or VSS
3
6
NC or VDD
VSS
4
5
27 MHz
Table 1. Pin Definitions for CY2410–1, –5
Name
Pin Number
Description
XIN
1
Reference crystal input
VDD
2
Voltage supply
VCXO
3
Input analog control for VCXO
VSS
4
Ground
27 MHz
5
27-MHz clock output
NC/VDD
6
No Connect or voltage supply
NC/VSS
7
No Connect or ground
XOUT[1]
8
Reference crystal output
Note
1. Float XOUT if XIN is externally driven.
Document #: 38-07317 Rev. *E
Page 2 of 8
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CY2410
Pullable Crystal Specifications [2]
Parameter
Description
Condition
Min
Typ.
Max
Unit
–
13.5
–
MHz
–
14
–
pF
–
–
25
Ω
3
–
–
–
0.5
2.0
FNOM
Nominal crystal frequency
CLNOM
Nominal load capacitance
R1
Equivalent series resistance (ESR)
R3/R1
Ratio of third overtone mode ESR to fundamental Ratio used because typical
mode ESR
R1 values are much less than
the maximum spec.
DL
Crystal drive level
No external series resistor
assumed
F3SEPHI
Third overtone separation from 3*FNOM
High side
300
–
–
ppm
F3SEPLO
Third overtone separation from 3*FNOM
Low side
–
–
–150
ppm
pF
Parallel resonance, fundamental mode, AT cut
Fundamental mode
mW
C0
Crystal shunt capacitance
–
–
7
C0/C1
Ratio of shunt to motional capacitance
180
–
250
C1
Crystal motional capacitance
14.4
18
21.6
pF
Note
2. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC.
Document #: 38-07317 Rev. *E
Page 3 of 8
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CY2410
Figure 2. Data Valid and Data Transition Periods
Data Valid
Transition
to next bit
SDAT
tDH
SCLK
tSU
CLKHIGH
VIH
CLKLOW
VIL
Figure 3. Start and Stop Frame
SDAT
SCLK
Transition
to next bit
START
STOP
Figure 4. Duty Cycle Definition; DC = t2/t1
t1
t2
CLK
50%
50%
Figure 5. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3, EF = 0.6 x VDD / t4
t4
t3
80%
CLK
Document #: 38-07317 Rev. *E
20%
Page 4 of 8
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CY2410
Absolute Maximum Conditions
Parameter
Description
Min
Max
Unit
VDD
Supply Voltage
–0.5
7.0
V
TS
Storage Temperature[3]
–65
125
°C
TJ
Junction Temperature
–
125
°C
Digital Inputs
VSS – 0.3
VDD + 0.3
V
Digital Outputs referred to VDD
VSS – 0.3
VDD + 0.3
Electrostatic Discharge
2000
V
V
Recommended Operating Conditions
Parameter
Description
Min
Typ.
Max
Unit
VDD
Operating Voltage
3.135
3.3
3.465
V
TA
Ambient Temperature
0
–
70
°C
CLOAD
Max. Load Capacitance
–
–
15
pF
fREF
Reference Frequency
–
13.5
–
MHz
tPU
Power up time for VDD to reach minimum specified voltage
(power ramp must be monotonic)
0.05
–
500
ms
Min
Typ.
Max
Unit
DC Electrical Specifications
Parameter
Name
Description
IOH
Output HIGH Current –1,–5
VOH = VDD – 0.5, VDD = 3.3V
12
24
–
mA
IOL
Output LOW Current –1,–5
VOL = 0.5, VDD = 3.3V
12
24
–
mA
CIN
Input Capacitance
–
–
7
pF
IIZ
Input Leakage Current
–
5
–
μA
fΔXO
VCXO pullability range:–1,–5
+150
–
–
ppm
VVCXO
VCXO input range
0
–
VDD
V
IVDD
Supply Current
–
30
35
mA
Min
Typ.
Max
Unit
AC Electrical Specifications (VDD = 3.3V)[4]
Parameter[4]
Name
Description
DC
Output Duty Cycle
Duty Cycle is defined in Figure 4, 50% of VDD
45
50
55
%
EROR
Rising Edge Rate –1, –5
Output Clock Edge Rate, Measured from
20% to 80% of VDD, CLOAD = 15 pF See
Figure 5.
0.8
1.4
–
V/ns
EROF
Falling Edge Rate –1, –5
Output Clock Edge Rate, Measured from
80% to 20% of VDD, CLOAD = 15 pF See
Figure 5.
0.8
1.4
–
V/ns
t9
Clock Jitter –1, –5
Peak-to-peak period jitter
–
140
–
ps
t10
PLL Lock Time
–
–
3
ms
Notes
3. Rated for ten years.
4. Not 100% tested.
Document #: 38-07317 Rev. *E
Page 5 of 8
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CY2410
Figure 6. Test and Measurement Setup
VDD
CLK out
0.1 μF
OUTPUTS
CLOAD
GND
Document #: 38-07317 Rev. *E
Page 6 of 8
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CY2410
Ordering Information
Ordering Code
Operating
Range
Package Type
Operating
Voltage
Features
Pb-Free
CY2410SXC–1[5]
8-pin SOIC
Commercial
3.3V
Linear VCXO control curve
CY2410SXC–1T
8-pin SOIC - Tape and Reel
Commercial
3.3V
Linear VCXO control curve
CY2410SXC–5[5]
8-pin SOIC
Commercial
3.3V
Matches nonlinear MK3727A VCXO control
curve
CY2410SXC–5T[5]
8-pin SOIC - Tape and Reel
Commercial
3.3V
Matches nonlinear MK3727A VCXO control
curve
CY2410KSXC–5
8-pin SOIC
Commercial
3.3V
Matches nonlinear MK3727A VCXO control
curve
CY2410KSXC–5T
8-pin SOIC - Tape and Reel
Commercial
3.3V
Matches nonlinear MK3727A VCXO control
curve
[5]
Package Drawing and Dimensions
Figure 7. 8-Lead (150-Mil) SOIC
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
51-85066 *C
Note
5. Not recommended for new designs.
Document #: 38-07317 Rev. *E
Page 7 of 8
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CY2410
Document History Page
Document Title: CY2410 MPEG Clock Generator with VCXO
Document Number: 38-07317
REV.
ECN NO.
Submission
Date
Orig. of
Change
**
111553
02/12/02
CKN
Description of Change
New Data Sheet
*A
114937
09/24/02
CKN
Added -6 to data sheet, Advance Information to Final
*B
121418
12/06/02
CKN
Updated the Pullable Crystal Specifications table on page 2
*C
126905
06/17/03
RGL
Added -7 part to data sheet
Added new parameter on the Pullable Crystal table
Power up requirements added to the operating conditions
*D
131100
01/20/03
RGL
Added VCXO –7 pullability range in the DC Specs with min. value of ±115ppm
*E
2440886
See ECN
AESA
Updated template. Added Note “Not recommended for new designs.”
Added part number CY2410SXC-1, CY2410SXC-1T, CY2410SXC-5,
CY2410SXC-5T, CY2410KSXC–5, and CY2410KSXC–5T in ordering information table. Removed all part numbers for non-Pb-free packages (part
numbers beginning CY2410SC). Removed details specific to the -3, -4, -6 and
-7 versions.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07317 Rev. *E
Revised May 22, 2008
Page 8 of 8
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