CY24119SC-1

CY7C09079V/89V/99V CY7C09179V/89V/99V PRELIMINARY CY24119 MediaClock™ 27-MHz VCXO Clock Generator Features • Low-jitter, high-accuracy output • VCXO with analog adjust • 3.3V operation Part Number CY24119 CY24119-1 Outputs 1 1 Benefits • Meets critical timing requirements in complex system designs • Large ± 150 ppm range, better linearity Input Frequency Range 27-MHz pullable crystal per Cypress specification 27-MHz pullable crystal per Cypress specification Output Frequencies One copy of 27-MHz (3.3V) positive slope VCXO curve One copy of 27-MHz (3.3V) negative slope VCXO curve Logic Block Diagram 27 XIN XOUT OSC 27 MHz Pin Configuration CY24119,-1 8-pin SOIC XIN AVDD VCXO AVSS 1 2 3 4 8 7 6 5 XOUT VSS 27 MHz VDD VCXO AVDD VDD AVSS VSS Cypress Semiconductor Corporation Document #: 38-07200 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised October 8, 2003 PRELIMINARY Pin Summary Name AVDD VDD AVSS VSS XIN VCXO XOUT 27 MHz Pin Number 2 5 4 7 1 3 8 6 Analog Voltage Supply Output Voltage Supply Analog Ground Output Ground Reference Crystal Input Analog Control for VCXO Reference Crystal Output 27-MHz Clock Output Description CY24119 Absolute Maximum Conditions Parameter VDD TS TJ Storage Description Supply Voltage Temperature[1] Junction Temperature Electrostatic Discharge 2 Min. –0.5 –65 Max. 7.0 125 125 Unit V °C °C kV Recommended Operating Conditions Parameter VDD, AVDD TA CLOAD fREF tPU Description Operating Voltage Ambient Temperature Max Load Capacitance Reference Frequency Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 10 0.05 27 Min. 3.14 0 Typ. 3.3 Max. 3.47 70 15 30 500 Unit V °C pF MHz ms DC Electrical Characteristics Parameter IOH IOL CIN IIZ Name Output HIGH Current Output LOW Current Input Capacitance Input Leakage Current VCXO Pullability Range VCXO Input Range VCXO Input Bandwidth Supply Current Sum of Core and Output Current –150 0 DC to 200 13 5 +150 AVDD Description VOH = VDD – 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) Min. 12 12 Typ. 24 24 7 Max. Unit mA mA pF µA ppm V kHz mA f∆xo VVCXO fVBW IDD Pullable Crystal Specifications Parameter FNOM CLNOM R1 Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Fundamental mode Condition Parallel resonance, fundamental mode, AT cut Min. Typ. 27 14 25 Max. Unit MHz pF Ω Note: 1. Not 100% tested. Document #: 38-07200 Rev. *B Page 2 of 5 PRELIMINARY Pullable Crystal Specifications (continued) Parameter R3/R1 DL F3SEPHI F3SEPLO C0 C0/C1 C1 Description Condition Min. 3 Typ. CY24119 Max. Unit Ratio of third overtone mode ESR to fundamen- Ratio used because typical tal mode ESR R1 values are much less than the maximum spec. Crystal drive level Third overtone separation from 3.FNOM Third overtone separation from 3.FNOM Crystal shunt capacitance Ratio of shunt to motional capacitance Crystal motional capacitance No external series resistor assumed High side Low side 0.5 300 2.0 mW ppm –150 7 180 14.4 18 250 21.6 ppm pF pF AC Electrical Characteristics (VDD = 3.3V) Parameter[1] DC t3 t4 t9 Name Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate Clock Jitter t1 t2 27 MHz 50% 27 MHz Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20% – 80% of VDD Output Clock Fall Time, 80% – 20% of VDD Peak-to-Peak Period Jitter t3 80% 20% t4 Min. 45 0.8 0.8 Typ. 50 1.4 1.4 100 Max. 55 Unit % V/ns V/ns ps Figure 1. Duty Cycle Definition; DC = t2/t1 Figure 2. Rise and Fall Time Definitions AVDD 0.1 µF OUTPUTS CLK out CLOAD VDD 0.1 µF GND Test Circuit Ordering Information Ordering Code CY24119SC CY24119SCT CY24119SC-1 CY24119SC-1T Package Name S8 S8 S8 S8 Package Type 8-pin SOIC 8-pin SOIC – Tape and Reel 8-pin SOIC 8-pin SOIC – Tape and Reel Operating Range Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V Document #: 38-07200 Rev. *B Page 3 of 5 PRELIMINARY Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID CY24119 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07200 Rev. *B Page 4 of 5 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document History Page Document Title: CY24119 MediaClock™ 27-MHz VCXO Clock Generator Document Number: 38-07200 REV. ** *A *B ECN NO. 111551 121877 129724 Issue Date 03/22/02 12/14/02 10/09/03 Orig. of Change CKN RBI IJA New Data Sheet Description of Change CY24119 Power-up requirements added to Operating Conditions Information Added -1 part, updated Crystal Spec Table Document #: 38-07200 Rev. *B Page 5 of 5