CY2412SXC-3T

CY2412 MPEG Clock Generator with VCXO Features Benefits ■ Integrated phase-locked loop (PLL) ■ Highest-performance PLL tailored for multimedia applications ■ Low-jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs ■ VCXO with analog adjust ■ Large ± 150-ppm range, better linearity ■ 3.3V operation ■ Enables application compatibility ■ 8-pin SOIC package Part Number Outputs CY2412-1 3 13.5-MHz pullable crystal input per Cypress specification Input Frequency Range Two 27 MHz outputs, one 54 MHz (3.3V) Linear Output Frequencies VCXO Profile CY2412-3 3 13.5-MHz pullable crystal input per Cypress specification 27 MHz, 13.5 MHz, 54 MHz (3.3V) Linear Logic Block Diagram CLKC 13.5 XIN OSC Φ Q XOUT OUTPUT DIVIDERS VCO CLKA P VCXO CLKB PLL VSS VDD Pin Configuration Figure 1. CY2412, 8-Pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 3 6 CLKC CLKB VSS 4 5 CLKA Table 1. Pin Definition - CY2412, 8-Pin SOIC Pin Name Pin Number Pin Description XIN 1 Reference Crystal Input VDD 2 Voltage Supply VCXO 3 Input Analog Control for VCXO VSS 4 Ground CLKA 5 54-MHz clock output CLKB 6 13.5-MHz clock output CLKC 7 27-MHz clock output XOUT[2] 8 Reference Crystal Output Cypress Semiconductor Corporation Document #: 38-07227 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 05, 2008 [+] Feedback CY2412 Pullable Crystal Specifications[1] Parameter Description Condition Min Typ. Max Unit Parallel resonance, fundamental mode, AT cut – 13.5 – MHz – 14 – pF Fundamental mode – – 25 Ω FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR to funda- Ratio used because typical R1 mental mode ESR values are much less than the maximum spec. 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2.0 mW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 pF Absolute Maximum Conditions Parameter Description VDD Supply Voltage Temperature[3] TS Storage TJ Junction Temperature Min Max Unit –0.5 7.0 V –65 125 °C – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V Electrostatic Discharge 2 kV Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min Typ. Max Unit 3.14 3.3 3.47 V 0 70 °C 15 pF 13.5 0.05 MHz 500 ms Max Unit DC Electrical Characteristics Parameter Description Test Conditions Min Typ. IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 mA CIN Input Capacitance IIZ Input Leakage Current 7 5 pF μA Notes 1. Crystals that meet this specification includes: Ecliptek ECX-5788-13.500M,Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL,PDI HA13500XFSA14XC. 2. Float XOUT if XIN is externally driven. 3. Rated for ten years. Document #: 38-07227 Rev. *F Page 2 of 5 [+] Feedback CY2412 DC Electrical Characteristics (continued) Parameter Description Test Conditions fΔXO VCXO pullability range VVCXO VCXO input range fVBW VCXO input bandwidth IDD Supply Current Min Typ. Max +150 Unit ppm 0 VDD DC to 200 Sum of Core and Output Current V kHz 35 mA Typ. Max Unit 55 AC Electrical Characteristics Parameter[4] Description Test Conditions Min DC Output Duty Cycle Duty Cycle is defined in Figure 2, 50% of VDD 45 50 ER Rising Edge Rate Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 3. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 3. 0.8 1.4 V/ns t9 Clock Jitter Peak to Peak period jitter t10 PLL Lock Time 100 % 200 ps 3 ms Figure 2. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% Figure 3. Rise and Fall Time Definitions: ER = 0.6 x VDD / t3 , EF = 0.6 x VDD / t4 t3 t4 80% CLK 20% Figure 4. Test Circuit VDD CLK out 0.1 μF OUTPUTS CLOAD GND Notes 4. Not 100% tested. Document #: 38-07227 Rev. *F Page 3 of 5 [+] Feedback CY2412 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY2412SC-1[5] 8-pin SOIC Commercial 3.3V CY2412SC-1T[5] 8-pin SOIC–Tape and Reel Commercial 3.3V CY2412SC-3[5] 8-pin SOIC Commercial 3.3V CY2412SC-3T[5] 8-pin SOIC–Tape and Reel Commercial 3.3V CY2412SXC-1[5] 8-pin SOIC Commercial 3.3V CY2412SXC-1T[5] 8-pin SOIC–Tape and Reel Commercial 3.3V CY2412SXC-3[5] 8-pin SOIC Commercial 3.3V CY2412SXC-3T[5] 8-pin SOIC–Tape and Reel Commercial 3.3V CY2412KSXC-1 8-pin SOIC Commercial 3.3V CY2412KSXC-1T 8-pin SOIC–Tape and Reel Commercial 3.3V Pb-Free Package Diagram ) Figure 5. 8-Lead (150-Mil) SOIC S8 ( PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C 0.0138[0.350] 0.0192[0.487] Note 5. Not recommended for new designs. Document #: 38-07227 Rev. *F Page 4 of 5 [+] Feedback CY2412 Document History Page Document Title: CY2412 MPEG Clock Generator with VCXO Document Number: 38-07227 REV. ECN Orig. of Change Submission Date ** 110492 SZV 10/28/01 Change from Spec number: 38-00898 to 38-07227 *A 112457 CKN 03/14/02 Added CY2412-2 to data sheet *B 116961 CKN 08/06/02 Removed CY2412-2 from the datasheet. Added CY2412-3 to data sheet Description of Change *C 121879 RBI 12/14/02 Power up requirements added to Operating Conditions Information *D 299735 RGL 02/15/05 Added lead-free for CY2412-1 and CY2412-3 devices *E 2440866 AESA 04/25/08 Updated template. Added Note “Not recommended for new designs.” Added part number CY2412KSXC-1, and CY2412KSXC-1T in ordering information table. Replaced Lead-Free with Pb-Free. *F 2512734 AESA 06/05/08 Added border to Logic Block Diagram. Added Sales, Solutions, and Legal Information. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. 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Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07227 Rev. *F Revised June 05, 2008 Page 5 of 5 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback