CY24133ZC-1

PRELIMINARY CY24133 MediaClock™ Digital TV Clock Generator with VCXO Features • Low jitter, high-accuracy outputs • VCXO with analog adjust • 3.3V operation Benefits Meets critical timing requirements in complex system designs Large ±150-ppm range, better linearity Enables application compatibility Frequency Table Part Number CY24133-1 Outputs 2 Input Frequency Range 27-MHz pullable Crystal per Cypress Specification Output Frequency Range 3.072-, 4.096-, 6.144-, 11.2896-, 12.288-MHz-selectable output frequencies and 27-MHz reference output Logic Block Diagram XIN OSC XOUT Q Φ VCO P VCXO CLKOUT PLL Output Multiplexer and Dividers REFCLK FS0 FS1 FS2 ROM AVDD VDD AVSS VSS VDDL VSSL Pin Configuration CY24133-1 16-pin TSSOP XIN VDD AVDD VCXO AVSS VSSL FS2 FS1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT NC NC VSS REFCLK VDDL FS0 CLKOUT Cypress Semiconductor Corporation Document #: 38-07497 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 3, 2003 PRELIMINARY CY24133 Pin Description Name XIN VDD AVDD VCXO AVSS VSSL FS2 FS1 CLKOUT FS0 VDDL REFCLK VSS NC NC XOUT [1] Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Description Reference Crystal Input Voltage Supply Analog Voltage Supply Input Analog Control Voltage for VCXO Analog Ground Output Clock Ground Frequency Select 2 Frequency Select 1 Configurable Clock Output 1 at VDDL level Frequency Select 0 Clock Output Voltage Supply Reference Clock Output at VDDL level Ground No Connect No Connect Reference Crystal Output Frequency Select Table—CY24133-1 FS2 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 FSO 0 1 0 1 0 1 0 1 CLKOUT 3.072 4.096 6.144 11.2896 12.288 off off off REFCLK 27 27 27 27 27 off off off Pullable Crystal Specifications Parameter CRload C0/C1 ESR To Crystal Accuracy TTs Equivalent Series Resistance Operating Temperature Crystal Accuracy Stability over temperature and aging 0 35 Name Crystal Load Capacitance Min. Typ. 14 250 50 70 +20 +50 Ω °C ppm ppm Max. Unit pF Absolute Maximum Conditions Parameter VDD VDDL TS TJ Description Supply Voltage I/O Supply Voltage Storage Temperature[2] Junction Temperature Min. –0.5 –0.5 –65 Max. 7.0 7.0 125 125 Unit V V °C °C Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07497 Rev. ** Page 2 of 5 PRELIMINARY Absolute Maximum Conditions (continued) Parameter Description Digital Inputs Analog Input referred to AVDD Electrostatic Discharge Min. AVSS – 0.3 AVSS – 0.3 2 Max. AVDD + 0.3 AVDD + 0.3 CY24133 Unit V V kV Recommended Operating Conditions Parameter AVDD/VDD/VDDL TA CLOAD fREF Description Operating Voltage Ambient Temperature Max. Load Capacitance VDD/VDDL=3.3V Reference Frequency 27 Min. 3.135 0 Typ. 3.3 Max. 3.456 70 15 Unit V °C pF MHz DC Electrical Specifications Parameter[3] IOH IOL VIH VIL CIN f∆XO VVCXO IDD Name Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance VCXO pullability range VCXO input range Supply Current AVDD/VDD/VDDL Current Description VOH = VDD – 0.5, VDD/VDDL = 3.3V VOL = 0.5, VDD/VDDL = 3.3V CMOS levels CMOS levels Frequency Select Pins +150 0 18 AVDD 25 Min. 12 12 0.7 0.3 7 Typ. 24 24 Max. Unit mA mA VDD VDD pF ppm V mA AC Electrical Specifications Parameter[3] DC ER EF t9 t10 Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 2. Peak-to-Peak period jitter on CLKOUT Measured from VDD = 3.0V Min. 45 0.8 0.8 Typ. 50 1.4 1.4 350 3 Max. 55 Unit % V/ns V/ns ps ms Test and Measurement Set-up VDDs 0.1 µF DUT Outputs CLOAD GND Note: 3. Guaranteed by design, not 100% tested. Document #: 38-07497 Rev. ** Page 3 of 5 PRELIMINARY Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V CY24133 Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD 20% of VDD 0V Clock Output Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code CY24133ZC-1 CY24133ZC-1T Package Name Z16 Z16 Package Type 16-pin TSSOP 16-pin TSSOP – Tape and Reel Operating Range Commercial Commercial Operating Voltage 3.3V 3.3V Package Drawing and Dimensions 16-lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16 51-85091-** MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07497 Rev. ** Page 4 of 5 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document History Page Document Title: CY24133 MediaClock™ Digital TV Clock Generator with VCXO Document Number: 38-07497 REV. ** ECN NO. Issue Date 121554 02/17/03 Orig. of Change CKN New Data Sheet Description of Change CY24133 Document #: 38-07497 Rev. ** Page 5 of 5