CY24141-3

PRELIMINARY CY24141-3 MediaClock™ Graphics Clock Generator Features • Integrated phase-locked loop (PLL) • Low-jitter, high-accuracy output • 3.3V operation with 2.5V/1.68V output • Ultra-linear crystal capacitors Part Number CY24141-3 Outputs 2 Input Frequency Range 18.432 MHz Benefits High-performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Enables application compatibility Ensures 0PPM Accuracy Output Frequencies 18.432 MHz, 53.94605395 MHz/54 MHz (selectable) Logic Block Diagram CLK_A 18.432 MHz XIN OSC XOUT Q Φ VCO P OUTPUT DIVIDER CLK_B (selectable) PLL FS AVDD VDDL AVSS VSSL VDD VSS Pin Configurations CY24141ZC-3 16-pin TSSOP XIN VDD AVDD FS AVSS VSSL N/C N/C 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK_A N/C VSS N/C VDDL N/C CLK_B CY24141 Frequency Select Table Frequency Select 1 0 PPM –1.000073 0 CLK_B 53.94605395 54 Unit MHz MHz Cypress Semiconductor Corporation Document #: 38-07324 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 4, 2002 PRELIMINARY Pin Summary Pin Name XIN VDD AVDD FS AVSS VSSL N/C N/C CLK_B N/C VDDL N/C VSS N/C CLK_A XOUT[1] Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Description Reference Input Voltage Supply Analog Voltage Supply Frequency Select Pin (Internal Pull-down Resistor) Analog Ground Output Ground No Connect No Connect CY24141-3 53.94605395-MHz/54-MHz Clock Output (Frequency Selectable) @ VDDL level No Connect Output Voltage Supply for CLK_B No Connect Ground No Connect 18.432-MHz Clock Output Reference Output Absolute Maximum Conditions Parameter AVDD TS TJ Description Supply Voltage Storage Temperature[2] Junction Temperature Digital Inputs Digital Outputs referred to VDD Electrostatic Discharge Recommended Operating Conditions Parameter AVDD VDD VDDLH VDDLL TA CLOAD fREF Note: Min. –0.5 –65 VSS – 0.3 VSS – 0.3 Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 2000 Unit V °C °C V V V Description Analog Voltage Supply Voltage Supply 2.5V Output Voltage Supply 1.68V Output Voltage Supply Ambient Temperature Max Load Capacitance Reference Frequency Min. 3.15 3.15 2.25 1.63 0 Typ. 3.45 3.45 2.5 1.68 Max. 3.6 3.6 2.75 1.75 85 15 Unit V V V V °C pF MHz 18.432 1. Float XOUT if XIN is externally driven. 2. Rated for 10 years. Document #: 38-07324 Rev. ** Page 2 of 6 PRELIMINARY DC Electrical Characteristics Parameter IOH3.3 IOL3.3 IOH2.5 IOL2.5 IOH1.68 IOL1.68 VIH VIL RI CIN XLDCAP IIZ IDD Parameter t9 t9 t9 t9 t9 Description Output High Current Output Low Current Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Input Resistor Input Capacitance Crystal Load Capacitance Input Leakage Current Supply Current Description Clock Jitter–peak-peak Clock Jitter–peak-peak Clock Jitter–peak-peak Clock Jitter–peak-peak Clock Jitter–peak-peak Conditions VOH = VDD – 0.5, VDD = 3.3 V VOL = 0.5, VDD = 3.3 V VOH = VDDL – 0.5, VDDL = 2.5 V VOL = 0.5, VDDL = 2.5 V VOH = VDDL – 0.5, VDDL = 1.68 V VOL = 0.5, VDDL = 1.68 V FS Frequency Select Input FS Frequency Select Input FS Frequency Select Pull Down Resistor Internal Load Caps Sum of Core and Output Current Conditions Cycle-Cycle Jitter–18.432 MHz Cycle-Cycle Jitter–54 MHz VDDL = 1.63V–1.75V Cycle-Cycle Jitter–54 MHz VDDL = 2.25V–2.75V Cycle-Cycle Jitter–53.94605395 MHz VDDL = 1.63V–1.75V Cycle-Cycle Jitter–53.94605395 MHz VDDL = 2.25V–2.75V Conditions 1000-Cycle-Cycle Jitter–18.432 MHz 1000-Cycle-Cycle Jitter–54 MHz VDDL = 1.63V–1.75V 1000-Cycle-Cycle Jitter–54 MHz VDDL = 2.25V–2.75V 1000-Cycle-Cycle Jitter–53.94605395 MHz–VDDL = 1.63V–1.75V 1000-Cycle-Cycle Jitter–53.94605395 MHz–VDDL = 2.25V–2.75V Conditions 18.432 MHz @ 10-kHz offset 54 MHz @ 10-kHz offset 53.94605395 MHz @ 10-kHz offset 1σ 12 32 11 31 11 Typ. 55 135 70 160 70 Min. 12 12 8 8 6 6 70% 80 CY24141-3 Typ. 24 24 20 20 12 12 Max. Unit mA mA mA mA mA mA VDD VDD kohm pF pF µA mA Unit ps ps ps ps ps 100 12.9 5 30 30% 135 7 10 35 Max. 140 220 150 220 150 Cycle-Cycle Jitter Specifications (VDD = 3.15V–3.6V) 1000-cycle Jitter (VDD = 3.15V–3.6V) Parameter Description Clock Jitter–peak-peak t10 Clock Jitter–peak-peak t10 t10 t10 t10 Clock Jitter–peak-peak Clock Jitter–peak-peak Clock Jitter–peak-peak 1σ 19 55 50 293 290 Typ. 95 275 275 1025 1025 Max. 140 400 400 1200 1200 Unit ps ps ps ps ps Phase Noise Specifications Parameter Description Phase Noise Phase Noise Phase Noise Min. Typ. –119 –95 –92 Max. Unit dBc dBc dBc Unit ppm ppm AC Electrical Characteristics (VDD = 3.15V–3.6V) Description Parameter[3] Frequency Error Fppm Fppm Note: Frequency Error Conditions Min. Typ. Max. Part to Part (three lots tested on same board, PCB board ±5 ±10 can vary more than ±5 ppm) Over temperature from 0 to 85°C (crystal should not be ±2 ±5 heated for this test, only IC) 3. Not 100% tested. Document #: 38-07324 Rev. ** Page 3 of 6 PRELIMINARY AC Electrical Characteristics (VDD = 3.15V–3.6V) (continued) Parameter[3] DC t3 t4 t5 Description Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate PLL Lock Time Conditions Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20%–80% of VDD/ VDDL = 2.5V Output Clock Fall Time, 80%–20% of VDD/ VDDL = 2.5V CY24141-3 Min. Typ. Max. 45 50 55 0.8 1.4 0.8 1.4 3 Unit % V/ns V/ns ms Test Circuit AVDD 0.1 µF OUTPUTS CLK out CLOAD t1 t2 CLK VDD 0.1 µF GND 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 80% t4 CLK 20% Figure 2. Rise and Fall Time Definitions VDD 80% t5 Figure 3. PLL Lock Time Stable @ ±0.1% frequency ... t10 ... t10 Figure 5. 1000-Cycle Jitter t9A t9B Figure 4. Cycle-Cycle Jitter Ordering Information Ordering Code CY24141ZC-3 Package Name Z16 Package Type 16-TSSOP Operating Range Commercial Operating Voltage 3.3V Document #: 38-07324 Rev. ** Page 4 of 6 PRELIMINARY 16-lead Thin Shrunk Small Outline Package (4.40-MM Body) Z16 CY24141-3 51-85091 MediaClock is a trademark of Cypress Semiconductor. All products and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07324 Rev. ** Page 5 of 6 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document Title: CY24141-3 MediaClock™ Graphics Clock Generator Document Number: 38-07324 REV. ** ECN NO. 111593 Issue Date 04/30/02 Orig. of Change CKN Description of Change New Data Sheet CY24141-3 Document #: 38-07324 Rev. ** Page 6 of 6