CY24142ZC-01T

CY24142 MediaClock™ Multimedia Clock Generator Features • Integrated phase-locked loop (PLL) • Low-jitter, high-accuracy outputs • 3.3V operation Benefits • Integrated high-performance PLL eliminates the need for — external loop filter components • Meets critical timing requirements in complex system designs • Enables application compatibility Logic Block Diagram XIN XOUT P OSC. Q Φ VCO OUTPUT MULTIPLEXER AND DIVIDERS CLK1 13.5 MHz CLK2 54 MHz CLK3 18.432 MHz CLK4 18.432 MHz PLL OE1 OE2 VDDL VDD AVDD AVSS VSS VSSL Pin Configuration CY24142 16-pin TSSOP XIN VDD AVDD OE1 AVSS VSSL NC CLK1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 XOUT CLK4 CLK3 VSS NC VDDL OE2 CLK2 Frequency Table Part Number CY24142-01 Outputs 4 Input Frequency 18.432 Output Frequency Range 13.5 MHz, 54 MHz, 2 x 18.432 MHz Output Enable Options[1] OE2 0 0 1 1 OE1 0 1 0 1 CLK1 13.5 13.5 13.5 13.5 CLK2 OFF 54 OFF 54 CLK3 OFF 18.432 OFF 18.432 CLK4 OFF OFF 18.432 18.432 Unit MHz MHz MHz MHz Note: 1. Output driven LOW when “OFF.” Cypress Semiconductor Corporation Document #: 38-07532 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 19, 2005 CY24142 Pin Description Pin Name XIN VDD AVDD OE1 AVSS VSSL NC CLK1 CLK2 OE2 VDDL NC VSS CLK3 CLK4 XOUT Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Crystal Input. Voltage Supply. Analog Voltage Supply. Output Enable 1, 0 = CLK 2 and CLK3 off, 1 = CLK 2 and CLK3 on; weak internal pull-down. Analog Ground. VDDL Ground. No Connect; leave floating. 13.5-MHz Clock Output. 54-MHz Clock Output; controlled by OE1. Output Enable 2, 0 = CLK4 off, 1 = CLK4 on; weak internal pull-down. Voltage Supply. No Connect; leave floating. Ground. 18.432-MHz Buffered Reference Output, controlled by OE1. 18.432-MHz Buffered Reference Output, controlled by OE2. Crystal Output. Pin Description Layout Recommendations The XIN and XOUT traces and pads as well as the crystal should be placed away from any clock traces or noise sources. Noise coupling into the XIN and XOUT traces may cause start-up problems. A pad for a resistor to ground should be laid out on the XOUT trace to be stuffed if necessary, in case start-up issues occur. Document #: 38-07532 Rev. *B Page 2 of 7 CY24142 Absolute Maximum Conditions (Above which the useful life may be impaired. For user guidelines, not tested. Supply Voltage (VDD, AVDD, VDDL) ...................–0.5 to +7.0V DC Input Voltage...................................... –0.5V to VDD + 0.5 Storage Temperature (Non-Condensing).... –55°C to +125°C Junction Temperature ................................ –40°C to +125°C Data Retention @ Tj=125°C..................................> 10 years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883.................... 2000V Recommended Crystal Specifications Parameter FNOM CLNOM R1 R3/R1 DL Description Nominal crystal frequency Nominal load capacitance Equivalent series resistance (ESR) Fundamental mode 3 0.5 2 mW Comments Parallel resonance, fundamental mode, AT cut Min. Typ. 18.432 14 25 Max. Unit MHz pF Ω Ratio of third overtone mode ESR Ratio used because typical R1 values are much to fundamental mode ESR less than the maximum spec Crystal drive level No external series resistor assumed Recommended Operating Conditions Parameter VDD, AVDD, VDDL TA CLOAD TPU Supply Voltage Ambient Temperature Max. Load Capacitance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 Description Min. 3.15 0 Typ. 3.45 Max. 3.6 85 15 500 Unit V °C pF ms DC Electrical Specifications Parameter IOH IIH IIL VIH VIL IVDD IVDDL RDOWN CXTAL[2] [2] Description Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Pull-down resistor on Inputs Crystal Load Capacitance Conditions VOH = VDD – 0.5, VDD/VDDL = 3.45V VOL = 0.5, VDD/VDDL = 3.45V VIH = VDD VIL = 0V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current VDD = 3.15 to 3.6V, measured VIN = 3.45V Total effective load of internal load caps Min. 12 12 Typ. 24 24 Max. Unit mA mA IOL[2] 50 5 0.7 0.3 25 20 100 12.9 150 10 µA µA VDD VDD mA mA kΩ pF Cycle-Cycle Jitter Specifications (VDD = 3.15V – 3.6V) Parameter t9 t9 t9 Description Clock Jitter–peak-peak Clock Jitter–peak-peak Clock Jitter–peak-peak Conditions Cycle-Cycle Jitter–18.432 MHz Cycle-Cycle Jitter–54 MHz Cycle-Cycle Jitter–13.5 MHz 1σ 20 40 20 Typ. 120 150 120 Max. 200 250 200 Unit ps ps ps Note: 2. Guaranteed by characterization, not 100% tested. Document #: 38-07532 Rev. *B Page 3 of 7 CY24142 Test and Measurement Set-up VDDs 0.1 µF DUT Outputs CLOAD GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 VDD/VDDL/AVDD 3.15V t5 Figure 3. PLL Lock Time Output stable within PPM Spec. Document #: 38-07532 Rev. *B Page 4 of 7 CY24142 tcycle,i tcycle,i+1 t6 = tcycle,i - tcycle,i+1 Figure 4. 54MOUT, LCLK Cycle-to-Cycle Jitter 1000 cycles 1000 cycles ... t1000cycle,i ... t1000cycle,i+1 t7 = t1000cycle,i - t1000cycle,i+1 Figure 5. 54MOUT, LCLK 1000 Cycle Jitter Ordering Information Ordering Code Standard CY24142ZC-01 CY24142ZC-01T Lead-free CY24142ZXC-01 CY24142ZXC-01T 16-pin TSSOP 16-pin TSSOP – Tape and Reel Commercial Commercial 3.45V 3.45V 16-pin TSSOP 16-pin TSSOP – Tape and Reel Commercial Commercial 3.45V 3.45V Package Type Operating Range Operating Voltage Document #: 38-07532 Rev. *B Page 5 of 7 CY24142 Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05gms 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A MediaClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07532 Rev. *B Page 6 of 7 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY24142 Document History Page Document Title: CY24142 MediaClock™ Multimedia Clock Generator Document Number: 38-07532 REV. ** *A *B ECN No. 127352 130343 310574 Issue Date 09/08/03 10/13/03 See ECN Orig. of Change RGL RGL RGL New Data Sheet Changed the part number from CY24142-1 to CY24142-01. Added Lead-free Description of Change Document #: 38-07532 Rev. *B Page 7 of 7