CY241V8ASXC-01

CY241V08A-01,04 CY241V8A-01 MPEG Clock Generator with VCXO MPEG Clock Generator with VCXO Features Benefits ■ Integrated Phase-Locked Loop (PLL) ■ Digital VCXO control ■ Low Jitter, High Accuracy Outputs ■ Second source for existing designs ■ VCXO with Analog Adjust ■ Highest performance PLL tailored for multimedia applications ■ 3.3 V Operation ■ Meets critical timing requirements in complex system designs ■ Compatible with MK3727 (–1, –4) ■ Application compatibility for a wide variety of Designs ■ Enables Design compatibility ■ Lower Drive Strength settings (CY241V08A–04) CY241V08A-01, -04 Logic Block Diagram Selector Guide Part Number Outputs Input Frequency Range Output Frequencies VCXO Control Curve Other Features CY241V08A-01 1 13.5 MHz pullable crystal input 1 copy of 27 MHz linear according to Cypress specification Compatible with MK3727 CY241V08A-04 1 13.5 MHz pullable crystal input 1 copy of 27 MHz linear according to Cypress specification Same as CY241V08A-01 except lower drive strength settings Cypress Semiconductor Corporation Document Number: 38-07656 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 23, 2013 CY241V08A-01,04 CY241V8A-01 Pin Configurations Figure 1. 8-pin SOIC pinout CY241V08A-01, -04 Pin Descriptions Name Pin Number XIN 1 Reference crystal input Description VDD 2 Voltage supply VCXO 3 Input analog control for VCXO VSS 4 Ground 27 MHz 5 27 MHz clock output NC/VDD 6 No connect or voltage supply NC/VSS 7 No connect or ground XOUT 8 Reference crystal output Document Number: 38-07656 Rev. *G Page 2 of 10 CY241V08A-01,04 CY241V8A-01 Absolute Maximum Conditions Storage Temperature (Non-condensing) .................................... –55 C to +125 C Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Junction Temperature ............................. –40 C to +125 C Supply Voltage (VDD) ...................................... –0.5 to +7.0 V DC Input Voltage ................................ –0.5 V to VDD + 0.5 V Data Retention at Tj = 125 C ..............................> 10 years Package Power Dissipation ..................................... 350 mW ESD (Human Body Model) MIL-STD-883 ............... > 2000 V Pullable Crystal Specifications Parameter [1] Description Comments Parallel resonance, fundamental mode, AT cut Min Typ Max Unit – 13.5 – MHz – 14 – pF – – 25  3 – – – FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR Ratio used because typical R1 to fundamental mode ESR values are much less than the maximum spec DL Crystal drive level No external series resistor assumed 150 – – W F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 – C1 Crystal motional capacitance 14.4 18 21.6 fF Min Typ Max Unit 3.135 3.3 3.465 V 0 – 70 °C – – 15 pF 0.05 – 500 ms Fundamental mode Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Maximum Load Capacitance tPU Power up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) Note 1. Crystals that meet this specification include: Ecliptek ECX-5788-13.500M, Siward XTL001050A-13.5-14-400, Raltron A-13.500-14-CL, PDI HA13500XFSA14XC. Document Number: 38-07656 Rev. *G Page 3 of 10 CY241V08A-01,04 CY241V8A-01 DC Electrical Specifications Parameter Name Description Min Typ Max Unit IOH Output HIGH Current VOH = VDD – 0.5 V, VDD = 3.3 V 12 24 – mA IOL Output LOW Current VOL = 0.5 V, VDD = 3.3 V 12 24 – mA CIN Input Capacitance Except XIN, XOUT pins VVCXO VCXO Input Range fXO [2] IVDD VCXO Pullability Range – – 7 pF 0 – VDD V Low Side – – –115 ppm High Side 115 – – ppm – 30 35 mA Min Typ Max Unit Supply Current AC Electrical Specifications (VDD = 3.3 V) Parameter [3] Name Description DC Output Duty Cycle Duty Cycle is defined in Figure 3, 50% of VDD 45 50 55 % EROR Rising Edge Rate -01 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 4. 0.8 1.4 – V/ns EROF Falling Edge Rate -01 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF, See Figure 4. 0.8 1.4 – V/ns EROR Rising Edge Rate -04 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF, See Figure 4. 0.7 1.1 – V/ns EROF Falling Edge Rate -04 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF, See Figure 4. 0.7 1.1 – V/ns t9 Clock Jitter Peak-to-peak period jitter – – 100 ps t10 PLL Lock Time – – 3 ms Test and Measurement Setup Figure 2. Test and Measurement Setup VDD 0.1 F DUT Outputs C LOAD GND Notes 2. –115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. 3. Not 100% tested. Document Number: 38-07656 Rev. *G Page 4 of 10 CY241V08A-01,04 CY241V8A-01 Voltage and Timing Definitions Figure 3. Duty Cycle Definition t1 t2 VDD 50% of VDD Clock Output 0V Figure 4. ER = (0.6 x VDD)/t3, EF = (0.6 x VDD)/t4 t3 t4 V DD 80% of V DD Clock Output Document Number: 38-07656 Rev. *G 20% of V DD 0V Page 5 of 10 CY241V08A-01,04 CY241V8A-01 Ordering Information Ordering Code Package Type Operating Range Operating Voltage Features Pb-free CY241V8ASXC-01 8-pin SOIC Commercial 3.3 V Linear VCXO control curve CY241V8ASXC-01T 8-pin SOIC –Tape and Reel Commercial 3.3 V Linear VCXO control curve 8-pin SOIC Commercial 3.3 V Linear VCXO control curve Pure Sn CY241V8ASXC-1S Ordering Code Definitions CY 241V8A S X C - XX X X = blank or T blank = Tube; T = Tape and Reel Specific Configuration Code: XX = 01 or 1 Temperature Grade: C = Commercial = 0 °C to 70 °C Pb-free Package Type: S = 8-pin SOIC Base Part Number Company ID: CY = Cypress Document Number: 38-07656 Rev. *G Page 6 of 10 CY241V08A-01,04 CY241V8A-01 Package Diagrams Figure 5. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *F Document Number: 38-07656 Rev. *G Page 7 of 10 CY241V08A-01,04 CY241V8A-01 Acronyms Acronym Document Conventions Description Units of Measure ESD Electrostatic Discharge ESR Equivalent Series Resistance °C degree Celsius PLL Phase Locked Loop fF femtofarad SOIC Small Outline Integrated Circuit MHz megahertz VCXO Voltage Controlled Crystal Oscillator µF microfarad µW microwatt mA milliampere ms millisecond mW milliwatt ns nanosecond  ohm % percent pF picofarad ppm parts per million ps picosecond V volt Document Number: 38-07656 Rev. *G Symbol Unit of Measure Page 8 of 10 CY241V08A-01,04 CY241V8A-01 Document History Page Document Title: CY241V08A-01,04/CY241V8A-01, MPEG Clock Generator with VCXO Document Number: 38-07656 Rev. ECN No. Submission Date Orig. of Change ** 214069 See ECN RGL Description of Change New data sheet *A 220404 See ECN RGL Minor Change: To post on web *B 393122 See ECN RGL Added Lead-free device for -01 Added the CY241V8A-01 in the title *C 414184 See ECN RGL Minor Change: Deleted unnecessary text in the benefit section *D 455059 See ECN RGL Added Pure Sn parts for -01 *E 2759384 09/02/2009 TSAI Updated template Post to external web *F 2897423 03/22/10 CXQ Updated ordering information table. Removed part numbers, CY241V08ASC–01, CY241V08ASC–01T, CY241V08ASC–04, and CY241V08ASC–04T Updated package diagram. Updated copyright section. *G 4009177 05/23/2013 CINM Added Ordering Code Definitions. Updated Package Diagrams: spec 51-85066 – Changed revision from *D to *F. Added Acronyms and Units of Measure. Updated in new template. Completing Sunset Review. Document Number: 38-07656 Rev. *G Page 9 of 10 CY241V08A-01,04 CY241V8A-01 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2004-2013. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07656 Rev. *G Revised May 23, 2013 All products and company names mentioned in this document may be the trademarks of their respective holders. Page 10 of 10