CY241V8ASXC-02

THIS SPEC IS OBSOLETE Spec No: 38-07674 Spec Title: CY241V08A-02 MPEG Clock Generator with VCXO Preliminary Sunset Owner: Christopher Martin (CXQ) Replaced by: None PRELIMINARY CY241V08A-02 MPEG Clock Generator with VCXO Features • • • • Benefits Robust Oscillator Low-jitter, high-accuracy outputs VCXO with analog adjust 3.3V operation • Highest-performance oscillator tailored for multimedia applications • Meets critical timing requirements in complex system designs • Application compatibility for a wide variety of designs Frequency Table Part Number Outputs CY241V08A-02 1 Input Frequency Range Output Frequencies 27-MHz pullable crystal input One copy of 27 MHz per Cypress specification VCXO Control Curve linear Other Features Low Jitter Non-PLL Block Diagram 27 XIN XBUF/27MHz OSC XOUT VCXO VDD VSS Pin Configuration CY241V08A-02 8-pin SOIC XIN 1 8 XOUT VDD VCXO 2 7 NC or VSS 3 6 NC or VDD VSS 4 5 27 MHz Cypress Semiconductor Corporation Document Number : 38-07674 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 5, 2010 [+] Feedback PRELIMINARY CY241V08A-02 Pin Descriptions Name Pin Number Description XIN 1 Reference crystal input. VDD 2 Voltage supply. VCXO 3 Input analog control for VCXO. VSS 4 Ground. XBUF/27 MHz 5 27-MHz buffered crystal output. NC 6 No Connect or VDD. NC 7 No Connect or VSS XOUT 8 Reference crystal output. Document Number : 38-07674 Rev. *B Page 2 of 6 [+] Feedback PRELIMINARY Absolute Maximum Conditions CY241V08A-02 Data Retention @ Tj = 125C................................> 10 years Supply Voltage (VDD) ........................................–0.5 to +7.0V DC Input Voltage...................................... –0.5V to VDD + 0.5 Storage Temperature (Non-condensing)..... –55C to +125C Junction Temperature ................................ –40C to +125C Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883................. > 2000V (Above which the useful life may be impaired. For user guidelines, not tested.) Pullable Crystal Specifications[1] Parameter Description Comments Min. Typ. Max. Unit – 27 – MHz – 14 – pF Fundamental mode – – 25  Ratio used because typical R1 values are much less than the maximum spec 3 – – – No external series resistor assumed 150 – – W Third overtone separation from 3*FNOM High side 300 – – ppm Third overtone separation from 3*FNOM Low side – – –150 ppm – – 7 pF 180 – 250 – 18 21.6 fF FNOM Nominal crystal frequency Parallel resonance, fundamental mode, AT cut CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR DL Crystal drive level F3SEPHI F3SEPLO C0 Crystal shunt capacitance C0/C1 Ratio of shunt to motional capacitance C1 Crystal motional capacitance 14.4 Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance tPU Power-up time for all VDD pins to reach minimum specified voltage (power ramps must be monotonic) Min. Typ. Max. Unit 3.135 3.3 3.465 V 0 – 70 °C – – 15 pF 0.05 – 500 ms DC Electrical Specifications Min. Typ. Max. Unit IOH Parameter Output HIGH Current Name VOH = VDD – 0.5V, VDD = 3.3V Description 12 24 – mA IOL Output LOW Current VOL = 0.5V, VDD = 3.3V 12 24 – mA CIN Input Capacitance Except XIN, XOUT pins – – 7 pF VVCXO VCXO Input Range fXO[2] VCXO Pullability Range IVDD Supply Current 0 – VDD V Low Side – – –115 ppm High Side 115 – – ppm – – 35 mA AC Electrical Specifications (VDD = 3.3V) [3] Parameter[3] Min. Typ. Max. Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 1, 50% of VDD Description 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 – V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 – V/ns t9 Peak-to-peak Period Jitter 27-MHz Clock Jitter – – 100 ps Notes: 1. Crystals that meet this specification includes: Ecliptek ECX-5808-27.000M 2. –115/+115 ppm assumes 2.5 pF of additional board level load capacitance. This range will be shifted down with more board capacitance or shifted up with less board capacitance. 3. Not 100% tested. Document Number : 38-07674 Rev. *B Page 3 of 6 [+] Feedback PRELIMINARY CY241V08A-02 Test and Measurement Set-up VDD Outputs 0.1 F CLOAD DUT GND Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD 20% of V DD Clock Output 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code Package Type Operating Range Operating Voltage Features Lead-free CY241V8ASXC-02 8-pin SOIC Commercial 3.3V Linear VCXO control curve CY241V8ASXC-02T 8-pin SOIC – Tape and Reel Commercial 3.3V Linear VCXO control curve Document Number : 38-07674 Rev. *B Page 4 of 6 [+] Feedback PRELIMINARY CY241V08A-02 Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.150[3.810] 0.157[3.987] 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 SZ08.15 LEAD FREE PKG. 8 0.189[4.800] 0.196[4.978] 0.010[0.254] 0.016[0.406] SEATING PLANE X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product or company names mentioned in this document may be the trademarks of their respective holders. Document Number : 38-07674 Rev. *B Page 5 of 6 [+] Feedback PRELIMINARY CY241V08A-02 Document History Page Document Title: CY241V08A-02 MPEG Clock Generator with VCXO Document Number: 38-07674 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 222320 See ECN RGL New Data Sheet *A 338335 See ECN RGL Added Lead-free *B 2904784 04/05/2010 CXQ Inactive parts; obsolete data sheet Document Number : 38-07674 Rev. *B Page 6 of 6 © Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback