CY24204ZXC-3T

CY24204 MediaClock™ DTV, STB Clock Generator Features Benefits ■ Integrated phase-locked loop (PLL) ■ Internal PLL with up to 400-MHz internal operation ■ Low jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs ■ VCXO with Analog Adjust ■ Large ±150-ppm range, better linearity ■ 3.3V operation ■ Enables application compatibility Part Number Outputs Input Frequency Output Frequency Range CY24204-3 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable) CY24204-4 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased VCXO pull range) CY24204-5 4 27-MHz Crystal Input Two copies of 27-MHz reference clock output, two copies of 27/27.027/74.250/74.17582418 MHz (frequency selectable, Increased output drive strength) Logic Block Diagram XIN OSC. Q Φ VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P VCXO CLK1 CLK2 PLL REFCLK1 REFCLK2 (-3,-4,-5) FS0 FS1 OE VDDL Cypress Semiconductor Corporation Document #: 38-07450 Rev. *D • VDD AVDD 198 Champion Court AVSS • VSS VSSL San Jose, CA 95134-1709 • 408-943-2600 Revised May 22, 2008 [+] Feedback CY24204 Pin Configuration Figure 1. CY24204-3,4,5 16-Pin TSSOP 1 16 XOUT 2 15 13 OE FS1 VSS 12 CLK1 AVDD 3 VCXO 4 AVSS 5 VSSL 6 REFCLK2 7 REFCLK1 8 24204-,3,4,5 XIN VDD 14 11 VDDL 10 FS0 9 CLK2 Table 1. Pin Definition Name Pin Number Description XIN 1 Reference Crystal Input. VDD 2 Voltage Supply. AVDD 3 Analog Voltage Supply. VCXO 4 Input Analog Control for VCXO. AVSS 5 Analog Ground. VSSL 6 CLK Ground. REFCLK2 7 Reference Clock Output. REFCLK1 8 Reference Clock Output. CLK1 9 27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable). FS0 10 Frequency Select 0, Weak Internal Pull up. VDDL 11 CLK Voltage Supply. CLK2 12 27/27.027/74.250/74.17582418-MHz Clock Output (Frequency Selectable). VSS 13 Ground. FS1 14 Frequency Select 1, Weak Internal Pull up. OE 15 Output Enable, Weak Internal Pull up. XOUT 16 Reference Crystal Output. Frequency Select Options OE FS1 FS0 CLK1/CLK2[1] REFCLK 1/2 Unit 0 0 0 off 27 MHz 0 0 1 off 27 MHz 0 1 0 off 27 MHz 0 1 1 off 27 MHz 1 0 0 27 27 MHz 1 0 1 27.027 27 MHz 1 1 0 74.250 27 MHz 1 1 1 74.17582418 27 MHz Note 1. “off” = output is driven HIGH. Document #: 38-07450 Rev. *D Page 2 of 7 [+] Feedback CY24204 Maximum Ratings Exceeding maximum ratings may impair the useful life of the Junction Temperature ................................. –40°C to +125°C device. These user guidelines are not tested. Data Retention at Tj=125°C ..................................> 10 years Supply Voltage (VDD, AVDDL, VDDL) ................. –0.5 to +7.0V Package Power Dissipation...................................... 350 mW DC Input Voltage ......................................–0.5V to VDD + 0.5 ESD (Human Body Model) MIL-STD-883.................... 2000V Storage Temperature (Non-Condensing).... –55°C to +125°C Pullable Crystal Specifications Parameter Description Comments Min Typ. Max Unit – 27.0 – MHz – 14 – pF 25 Ω FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) Fundamental mode – R3/R1 Ratio of third overtone mode ESR to fundamental mode ESR Ratio used because typical R1 values are much less than the maximum spec 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2 mW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 fF Min Typ. Max Unit 3.135 3.3 3.465 V Parallel resonance, fundamental mode, AT cut Recommended Operating Conditions Parameter Description VDD/AVDDL/VDDL Operating Voltage TA Ambient Temperature 0 – 70 °C CLOAD Max. Load Capacitance – – 15 pF tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 – 500 ms DC Electrical Specifications Parameter[1] Min Typ. Max Unit IOH1 Output High Current for -3,-4, Name VOH = VDD – 0.5, VDD/VDDL = 3.3V Description 12 24 – mA IOL1 Output Low Current for -3,-4 VOL = 0.5, VDD/VDDL = 3.3V 12 24 – mA IOH2 Output High Current for -5 VOH = VDD – 0.5, VDD/VDDL = 3.3V 18 26 – mA IOL2 Output Low Current for -5 VOL = 0.5, VDD/VDDL = 3.3V 18 26 – mA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – – VDD VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3 VDD IVDD Supply Current AVDD/VDD Current – – 25 mA IVDDL Supply Current VDDL Current (VDDL = 3.47V) – – 20 mA CIN Input Capacitance – – 7 pF Note 1. Not 100% tested. Document #: 38-07450 Rev. *D Page 3 of 7 [+] Feedback CY24204 DC Electrical Specifications (continued) Parameter[1] Name Description fΔXO VCXO pullability range Nominal pullability for -3,-5 fΔXO VCXO pullability range Extended pullability for -4 VVCXO VCXO input range RUP Pull up resistor on inputs Min Typ. Max Unit ±150 – – ppm – ±200 – ppm 0 – VDD V – 100 150 kΩ Min Typ. Max Unit 45 50 55 % VDD = 3.14 to 3.47V, measured at VIN = 0V AC Electrical Specifications Parameter[1] Name Description DC Output Duty Cycle Duty Cycle is defined in Figure 3; t1/t2, 50% of VDD ER1 Rising Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 4. 0.8 1.4 – V/ns EF1 Falling Edge Rate for -3,-4 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 4. 0.8 1.4 – V/ns ER2 Rising Edge Rate for -5 Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF See Figure 4. 1.0 1.8 – V/ns EF2 Falling Edge Rate for -5 Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF See Figure 4. 1.0 1.8 – V/ns t9 Clock Jitter CLK1, CLK2 Peak-Peak period jitter – 120 – ps t10 PLL Lock Time – – 3 ms Figure 2. Test and Measurement Setup VDDs Outputs 0.1 μF DUT CLOAD GND Voltage and Timing Definitions Figure 3. Duty Cycle Definition t1 t2 VDD 50% of VDD Clock Output Document #: 38-07450 Rev. *D 0V Page 4 of 7 [+] Feedback CY24204 Figure 4. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Ordering Information Package Name Package Type Operating Range Operating Voltage CY24204ZXC-3[2] ZZ16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-3T[2] ZZ16 16-Pin TSSOP-Tape and Reel Commercial 3.3V CY24204ZXC-4[2] ZZ16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-4T[2] ZZ16 16-Pin TSSOP-Tape and Reel Commercial 3.3V CY24204ZXC-5[2] ZZ16 16-Pin TSSOP Commercial 3.3V CY24204ZXC-5T[2] ZZ16 16-Pin TSSOP-Tape and Reel Commercial 3.3V CY24204KZXC-3 ZZ16 16-Pin TSSOP Commercial 3.3V CY24204KZXC-3T ZZ16 16-Pin TSSOP-Tape and Reel Commercial 3.3V Ordering Code Pb-Free Note 2. Not recommended for new designs. Document #: 38-07450 Rev. *D Page 5 of 7 [+] Feedback CY24204 Package Drawing Figure 5. 16-Lead TSSOP 4.40mm Body 16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. 1 MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05gms 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] Document #: 38-07450 Rev. *D 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A Page 6 of 7 [+] Feedback CY24204 Document History Page Document Title: CY24204 MediaClock™ DTV, STB Clock Generator Document Number: 38-07450 REV. ECN NO. Submission Date Orig. of Change ** 123842 04/10/03 CKN *A 128775 09/0803 IJA *B 214080 See ECN RGL Added -6 part *C 310573 See ECN RGL Removed -1,-2 and -6 parts Added Lead-free devices for -3, -4, and -5 parts *D 2440886 See ECN Description of Change New Data Sheet Added -4 and -5 parts KVM/AESA Updated template. Added Note “Not recommended for new designs.” Added part number CY24204KZXC-3, and CY24204KZXC-3T in ordering information table. Removed non-Pb-free part numbers (those beginning CY24204ZC). Replaced “Lead-free” with “Pb-Free”. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2003-2008. The information contained herein is subject to change without notice. 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Document #: 38-07450 Rev. *D Revised May 22, 2008 Page 7 of 7 MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback