CY24206ZXC-4T

CY24206 MediaClock™ DTV, STB Clock Generator Features Benefits • Integrated phase-locked loop (PLL) • Internal PLL with up to 400-MHz internal operation • Meets critical timing requirements in complex system designs • Enables application compatibility • Low-jitter, high-accuracy outputs • 3.3V operation • Available in 16-pin TSSOP Package Part Number Outputs Input Frequency CY24206-1 3 27 MHz 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) Output Frequency Range CY24206-2 4 27 MHz 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.175-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) CY24206-3 4 27 MHz 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) CY24206-4 4 27 MHz 1 copy 27-MHz reference clock output 1 copy of 81-/81.081-/74.17582-/74.250-MHz (frequency selectable) 1 copy of 27-/27.027-/24.725-/24.75-MHz (frequency selectable) 1 copy of 27-/27.027-/74.175-/74.25-MHz (frequency selectable) Logic Block Diagram XIN OSC. Q Φ VCO XOUT OUTPUT MULTIPLEXER AND DIVIDERS P CLK1 CLK2 PLL REFCLK FS0 CLK3 (-2, -3,-4) FS1 FS2 OE VDDL Pin Configurations CY24206-1 16-pin TSSOP VDD AVDD AVSS VSS VSSL CY24206-2,3,4 16-pin TSSOP XIN VDD 1 16 XOUT 16 XOUT 15 2 15 AVDD 3 14 AVDD 3 14 OE 4 13 FS2 FS1 VSS XIN VDD 1 2 OE 4 13 FS2 FS1 VSS AVSS 5 12 N/C AVSS 5 12 CLK3 VSSL 6 11 VDDL VSSL 6 11 VDDL CLK1 CLK2 7 10 CLK1 CLK2 10 9 FS0 REFCLK 7 8 8 9 FS0 REFCLK Cypress Semiconductor Corporation Document #: 38-07451 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 27, 2004 [+] Feedback CY24206 Frequency Select Options FS2 FS1 FS0 CLK1 (-1,-2) CLK1 (-3,-4) CLK2 CLK3 (-2, -3,-4) REFCLK Units 0 0 0 81 81 27 (CLK1/3) 27 (CLK1/3) 27 MHz 0 0 1 81.081 81.081 27.027 (CLK1/3) 27.027 (CLK1/3) 27 MHz 0 1 0 74.175 74.17582 24.725 (CLK1/3) 74.17582 (CLK1) 27 MHz 0 1 1 74.250 74.25 24.75 (CLK1/3) 74.25 (CLK1) 27 MHz 1 0 0 81 81 27 27 (CLK1/3) 27 MHz 1 0 1 81.081 81.081 27 27.027 (CLK1/3) 27 MHz 1 1 0 74.175 74.1758 27 74.175 (CLK1) 27 MHz 1 1 1 74.250 74.25 27 74.25 (CLK1) 27 MHz Pin Description Name Pin Number Description XIN 1 Reference Crystal Input. VDD 2 Voltage Supply. AVDD 3 Analog Voltage Supply. OE 4 Output Enable, weak internal pull-up. 0 = outputs off, 1 = outputs on. AVSS 5 Analog Ground. VSSL 6 VDDL Ground. CLK1 (-1,-2) 7 81-/81.081-/74.175-/74.250-MHz Clock Output (frequency selectable). CLK1 (-3,-4) 7 81-/81.081-/74.17582-/74.25-MHz Clock Output (frequency selectable). CLK2 8 27-/27.027-/24.725-/24.75-MHz Clock Output (frequency selectable). REFCLK 9 Reference Clock Output. FS0 10 Frequency Select 0, weak internal pull-up. VDDL 11 Voltage Supply. N/C (-1) 12 No Connect. CLK3 (-2,-3,-4) 12 27-/27.027-/74.175-/74.25-MHz Clock Output (frequency selectable). VSS 13 Ground. FS1 14 Frequency Select 1, weak internal pull-up. FS2 15 Frequency Select 2, weak internal pull-up. XOUT 16 Reference Crystal Output. Document #: 38-07451 Rev. *B Page 2 of 6 [+] Feedback CY24206 Absolute Maximum Conditions Parameter Description VDD Supply Voltage VDDL I/O Supply Voltage TJ Junction Temperature Min. Max. –0.5 Digital Inputs AVSS – 0.3 Electrostatic Discharge Unit 7.0 V 7.0 V 125 °C AVDD + 0.3 V 2 kV Recommended Operating Conditions Parameter Description VDD/AVDDL/VDDL Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance fREF Reference Frequency Min. Typ. Max. 3.135 3.3 3.465 V 70 °C 0 Unit 15 pF 27 MHz DC Electrical Specifications Parameter[1] Name Description Min. Typ. Max. Unit IOH Output High Current VOH = VDD – 0.5, VDD/VDDL = 3.3V 12 24 mA IOL Output Low Current VOL = 0.5, VDD/VDDL = 3.3V 12 24 mA IIH Input High Current VIH = VDD – 5 10 µA IIL Input Low Current VIL = 0V – – 50 µA 0.3 VDD VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD 0.7 VDD IVDD Supply Current AVDD/VDD Current 25 mA IVDDL Supply Current VDDL Current 20 mA RUP Pull-up resistor on Inputs VDD = 3.14 to 3.47V, measured VIN = 0V 100 150 kΩ Min. Typ. Max. Unit 55 % AC Electrical Specifications Parameter[1] Name Description DC Output Duty Cycle Duty Cycle is defined in Figure 1; t1/t2, 50% of VDD 45 50 ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. 0.8 1.4 V/ns t9 Clock Jitter CLK1, CLK2 Peak-Peak period jitter t10 PLL Lock Time 200 ps 3 ms Test and Measurement Set-up VDDs Outputs 0.1 µF DUT CLOAD GND Note: 1. Not 100% tested. Document #: 38-07451 Rev. *B Page 3 of 6 [+] Feedback CY24206 Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V Figure 1. Duty Cycle Definitions t4 t3 V DD 80% of V DD 20% of V DD Clock Output Ordering Information 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Code Package Name Package Type Operating Range Operating Voltage CY24206ZC-2 Z16 16-Pin TSSOP Commercial 3.3V CY24206ZC-2T Z16 16-Pin TSSOP – Tape and Reel Commercial 3.3V CY24206ZC-3 Z16 16-Pin TSSOP Commercial 3.3V CY24206ZC-3T Z16 16-Pin TSSOP – Tape and Reel Commercial 3.3V CY24206ZC-4 Z16 16-Pin TSSOP Commercial 3.3V CY24206ZC-4T Z16 16-Pin TSSOP – Tape and Reel Commercial 3.3V CY24206ZXC-4 Z16 16-Pin TSSOP Commercial 3.3V CY24206ZXC-4T Z16 16-Pin TSSOP – Tape and Reel Commercial 3.3V Lead Free Document #: 38-07451 Rev. *B Page 4 of 6 [+] Feedback CY24206 Package Drawing and Dimensions 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. MAX. 1 REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] PACKAGE WEIGHT 0.05 gms PART # 4.30[0.169] 4.50[0.177] Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091-*A MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07451 Rev. *B Page 5 of 6 [+] Feedback CY24206 Document History Page Document Title: CY24206 MediaClock™ DTV, STB Clock Generator Document Number: 38-07451 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 120901 12/10/02 CKN New data sheet *A 123046 03/03/03 CKN Added –4 to data sheet *B 270029 See ECN RGL Removed Preliminary Added Lead-free devices for -4 Document #: 38-07451 Rev. *B Page 6 of 6 [+] Feedback