CY24212KSXC-5

THIS SPEC IS OBSOLETE Spec No: 38-07402 Spec Title: CY24212 MEDIACLOCK(TM) MPEG CLOCK GENERATOR WITH VCXO PRELIMINARY Sunset Owner: Brijesh A Shah (BASH) Replaced by: None PRELIMINARY CY24212 MediaClock™ MPEG Clock Generator with VCXO Features Benefits ■ Integrated phase-locked loop (PLL) ■ Highest-performance PLL tailored for multimedia applications ■ Low jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs ■ VCXO with analog adjust ■ Large ±150-ppm range, better linearity ■ 3.3V operation ■ Enables application compatibility Logic Block Diagram XIN OUTPUT DIVIDERS OSC Q XOUT Φ CLKA (27 MHz) VCO 27 MHz (-2) 27/27.027 MHz (-3) P VCXO PLL FSEL VSS VDD Table 1. CY24212-5 Frequency Select Option FSEL Reference CLKA 0 27 MHz 27 MHz 27 MHz 1 27 MHz 27 MHz 27.027 MHz Cypress Semiconductor Corporation Document #: 38-07402 Rev. *F • 198 Champion Court CLKB • San Jose, CA 95134-1709 • 408-943-2600 Revised October 08, 2010 CY24212 PRELIMINARY Pin Configurations Figure 1. CY24212, 8-pin SOIC CY24212-5 CY24212-2 CY24212-1 XIN 1 8 XOUT VDD VCXO 2 7 VSS 3 6 VSS 4 5 FSEL CLKA 27 MHz XIN 1 8 XOUT VDD VCXO 2 7 CLKB 27 MHz 3 6 VSS 4 5 FSEL CLKA 27 MHz XIN 1 8 XOUT VDD VCXO 2 7 CLKB (27/27.027 MHz) 3 6 VSS 4 5 FSEL CLKA 27 MHz Table 2. Pin Definition Name XIN VDD VCXO VSS CLKA FSEL Pin Number 1 2 3 4 5 6 CLKB XOUT[1] 7 8 Description Reference Input. Voltage Supply. Input Analog Control for VCXO. Ground. 27-MHz Clock Output. Output Frequency Select, Weak Internal Pull up. FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz 27 MHz/27.027 MHz. Reference Output. Pullable Crystal Specifications Parameter CRload C0/C1 ESR To Crystal Accuracy TTs Name Crystal Load Capacitance Min Equivalent Series Resistance Operating Temperature Crystal Accuracy Stability over Temperature and Aging Typ. 14 35 0 Max 240 50 70 ± 20 ± 50 Unit pF Ω °C ppm ppm Absolute Maximum Conditions Parameter VDD TS TJ Description Supply Voltage Storage Temperature[2] Junction Temperature Digital Inputs Electrostatic Discharge Min –0.5 –65 Max 7.0 125 125 VDD + 0.3 VSS – 0.3 2 Unit V °C °C V kV Recommended Operating Conditions Parameter VDD TA CLOAD fREF Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency Min 3.135 0 13.5 Typ. 3.3 Max 3.465 70 15 27 Unit V °C pF MHz Notes 1. Float XOUT if XIN is externally driven. 2. Rated for ten years. Document #: 38-07402 Rev. *F Page 2 of 6 CY24212 PRELIMINARY DC Electrical Specifications Min Typ IOH Parameter Output High Current Name VOH = VDD – 0.5, VDD = 3.3V (source) Description 12 24 IOL Output Low Current VOL = 0.5, VDD = 3.3V (sink) 12 24 CIN Input Capacitance IIH Input High Current VIH = VDD – IIL Input Low Current VIL = 0V – fΔXO VCXO Pullability Range VVCXO VCXO Input Range IDD Supply Current Sum of Core and Output Current VIH Input High Voltage CMOS levels, 70% of VDD VIL Input Low Voltage CMOS levels, 30% of VDD RUP Pull up resistor on inputs VDD = 3.14 to 3.47V, measured VIN = 0V Max Unit mA mA 7 pF 5 10 μA – 50 μA ±150 ppm 0 VDD 35 0.7 V mA VDD 100 0.3 VDD 150 kΩ AC Electrical Specifications (VDD = 3.3V) Parameter[3] Min Typ Max Unit DC Output Duty Cycle Name Duty Cycle is defined in Figure 2, 50% of VDD Description 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 3. 0.8 1.4 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 3. 0.8 1.4 V/ns t9 Clock Jitter Peak-to-peak period jitter t10 PLL Lock Time 300 ps 3 ms Test and Measurement Setup VDDs Outputs 0.1 μF DUT CLOAD GND Note 3. Not 100% tested. Document #: 38-07402 Rev. *F Page 3 of 6 CY24212 PRELIMINARY Voltage and Timing Definitions Duty Cycle Figure Definition 2. t1 t2 VDD 50% of VDD Clock Output 0V Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 t4 t3 V DD 80% of V DD 20% of V DD Clock Output 0V Ordering Information Ordering Code Package Name Package Type Operating Range Operating Voltage S8 8-Pin SOIC Commercial 3.3V Pb-free CY24212KSXC-5 Note 4. Not recommended for new designs. Document #: 38-07402 Rev. *F Page 4 of 6 CY24212 PRELIMINARY Package Drawing and Dimensions Figure 4. 8-lead (150-Mil) SOIC S8 51-85066 *D Document #: 38-07402 Rev. *F Page 5 of 6 PRELIMINARY CY24212 Document History Page Document Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO Document Number: 38-07402 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 117089 09/09/02 CKN New Data Sheet *A 120888 12/06/02 CKN Added -3 *B 123064 02/19/03 CKN Added -5 *C 345540 See ECN RGL Added Pb-free for -5 part *D 2447126 See ECN AESA Updated template. Added Note “Not recommended for new designs.” Added part number CY24212KSXC-5 in ordering information table. *E 2902315 03/31/10 KVM Removed inactive parts from the ordering information table. Updated contents and package diagram. *F 3052224 10/08/2010 BASH Pruned part; obsolete datasheet © Cypress Semiconductor Corporation, 2002-2010. The information contained herein is subject to change without notice. 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Document #: 38-07402 Rev. *F Revised October 08, 2010 Page 6 of 6 MediaClock is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.