PRELIMINARY
CY24212
MediaClock™
MPEG Clock Generator with VCXO
Features
Benefits
■
Integrated phase-locked loop (PLL)
■
Highest-performance PLL tailored for multimedia applications
■
Low jitter, high-accuracy outputs
■
Meets critical timing requirements in complex system designs
■
VCXO with analog adjust
■
Large ±150-ppm range, better linearity
■
3.3V operation
■
Enables application compatibility
Part Number
Outputs
Input Frequency Range
CY24212-1
1
13.5 MHz/27 MHz (selectable)
27 MHz
Output Frequencies
CY24212-2
2
13.5 MHz/27 MHz (selectable)
Two copies of 27 MHz
CY24212-3
2
27 MHz
27 MHz/27.027 MHz (-1 ppm)
CY24212-5
2
27 MHz
27 MHz/27.027 MHz (0 ppm)
Logic Block Diagram
XIN
OUTPUT
DIVIDERS
OSC
Q
XOUT
Φ
CLKA (27 MHz)
VCO
27 MHz (-2)
27/27.027 MHz (-3)
P
VCXO
PLL
FSEL
VSS
VDD
Table 1. CY24212 (-1, -2) Frequency Select Option
FSEL
Reference
CLKA/CLKB
0
13.5 MHz
27 MHz
1
27 MHz
27 MHz
Table 2. CY24212 (-3, -5) Frequency Select Option
FSEL
Reference
CLKA
0
27 MHz
27 MHz
27 MHz
1
27 MHz
27 MHz
27.027 MHz
Cypress Semiconductor Corporation
Document #: 38-07402 Rev. *D
•
198 Champion Court
CLKB
•
San Jose, CA 95134-1709
•
408-943-2600
Revised April 25, 2008
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CY24212
PRELIMINARY
Pin Configurations
Figure 1. CY24212, 8-pin SOIC
CY24212-3,-5
CY24212-2
CY24212-1
XIN
1
8
XOUT
VDD
VCXO
2
7
VSS
3
6
VSS
4
5
FSEL
CLKA 27 MHz
XIN
1
8
XOUT
VDD
VCXO
2
7
CLKB 27 MHz
3
6
VSS
4
5
FSEL
CLKA 27 MHz
XIN
1
8
XOUT
VDD
VCXO
2
7
CLKB (27/27.027 MHz)
3
6
VSS
4
5
FSEL
CLKA 27 MHz
Table 3. Pin Definition
Name
XIN
VDD
VCXO
VSS
CLKA
FSEL (-1,-2)
Pin Number
1
2
3
4
5
6
FSEL (-3,-5)
6
VSS (-1)
CLKB (-2)
CLKB (-3,-5)
XOUT[1]
7
7
7
8
Description
Reference Input.
Voltage Supply.
Input Analog Control for VCXO.
Ground.
27-MHz Clock Output.
Input Frequency Select, Weak Internal Pull up.
FSEL = 0, XIN = 13.5 MHz
FSEL = 1, XIN = 27 MHz
Output Frequency Select, Weak Internal Pull up.
FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz
FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz
Ground.
27 MHz.
27 MHz/27.027 MHz.
Reference Output.
Pullable Crystal Specifications
Parameter
CRload
C0/C1
ESR
To
Crystal Accuracy
TTs
Name
Crystal Load Capacitance
Min
Equivalent Series Resistance
Operating Temperature
Crystal Accuracy
Stability over Temperature and Aging
Typ.
14
35
0
Max
240
50
70
± 20
± 50
Unit
pF
Ω
°C
ppm
ppm
Absolute Maximum Conditions
Parameter
VDD
TS
TJ
Description
Supply Voltage
Storage Temperature[2]
Junction Temperature
Digital Inputs
Electrostatic Discharge
Min
–0.5
–65
Max
7.0
125
125
VDD + 0.3
VSS – 0.3
2
Unit
V
°C
°C
V
kV
Recommended Operating Conditions
Parameter
VDD
TA
CLOAD
fREF
Description
Operating Voltage
Ambient Temperature
Max. Load Capacitance
Reference Frequency
Min
3.135
0
13.5
Typ.
3.3
Max
3.465
70
15
27
Unit
V
°C
pF
MHz
Notes
1. Float XOUT if XIN is externally driven.
2. Rated for ten years.
Document #: 38-07402 Rev. *D
Page 2 of 6
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CY24212
PRELIMINARY
DC Electrical Specifications
Min
Typ
IOH
Parameter
Output High Current
Name
VOH = VDD – 0.5, VDD = 3.3V (source)
Description
12
24
IOL
Output Low Current
VOL = 0.5, VDD = 3.3V (sink)
12
24
CIN
Input Capacitance
IIH
Input High Current
VIH = VDD
–
IIL
Input Low Current
VIL = 0V
–
fΔXO
VCXO Pullability Range
VVCXO
VCXO Input Range
IDD
Supply Current
Sum of Core and Output Current
VIH
Input High Voltage
CMOS levels, 70% of VDD
VIL
Input Low Voltage
CMOS levels, 30% of VDD
RUP
Pull up resistor on inputs
VDD = 3.14 to 3.47V, measured VIN = 0V
Max
Unit
mA
mA
7
pF
5
10
μA
–
50
μA
±150
ppm
0
VDD
35
0.7
V
mA
VDD
100
0.3
VDD
150
kΩ
AC Electrical Specifications (VDD = 3.3V)
Parameter[3]
Min
Typ
Max
Unit
DC
Output Duty Cycle
Name
Duty Cycle is defined in Figure 2, 50% of VDD
Description
45
50
55
%
ER
Rising Edge Rate
Output Clock Edge Rate, Measured from 20% to
80% of VDD, CLOAD = 15 pF. See Figure 3.
0.8
1.4
V/ns
EF
Falling Edge Rate
Output Clock Edge Rate, Measured from 80% to
20% of VDD, CLOAD = 15 pF. See Figure 3.
0.8
1.4
V/ns
t9
Clock Jitter
Peak-to-peak period jitter
t10
PLL Lock Time
300
ps
3
ms
Test and Measurement Setup
VDDs
Outputs
0.1 μF
DUT
CLOAD
GND
Note
3. Not 100% tested.
Document #: 38-07402 Rev. *D
Page 3 of 6
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CY24212
PRELIMINARY
Voltage and Timing Definitions
Figure 2. Duty Cycle Definition
t1
t2
VDD
50% of VDD
Clock
Output
0V
Figure 3. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
t4
t3
V
DD
80% of V DD
20% of V DD
Clock
Output
0V
Ordering Information
Ordering Code
Package Name
Package Type
Operating Range
Operating Voltage
S8
8-Pin SOIC
Commercial
3.3V
S8
8-Pin SOIC -Tape and Reel
Commercial
3.3V
S8
8-Pin SOIC
Commercial
3.3V
S8
8-Pin SOIC -Tape and Reel
Commercial
3.3V
S8
8-Pin SOIC
Commercial
3.3V
S8
8-Pin SOIC -Tape and Reel
Commercial
3.3V
S8
8-Pin SOIC
Commercial
3.3V
S8
8-Pin SOIC -Tape and Reel
Commercial
3.3V
S8
8-Pin SOIC
Commercial
3.3V
CY24212SXC-5T
S8
8-Pin SOIC -Tape and Reel
Commercial
3.3V
CY24212KSXC-5
S8
8-Pin SOIC
Commercial
3.3V
CY24212SC-1
[4]
CY24212SC-1T[4]
CY24212SC-2
[4]
CY24212SC-2T[4]
CY24212SC-3
[4]
CY24212SC-3T[4]
CY24212SC-5
[4]
CY24212SC-5T[4]
Pb-free
CY24212SXC-5[4]
[4]
Note
4. Not recommended for new designs.
Document #: 38-07402 Rev. *D
Page 4 of 6
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CY24212
PRELIMINARY
Package Drawing and Dimensions
Figure 4. 8-lead (150-Mil) SOIC S8
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document #: 38-07402 Rev. *D
Page 5 of 6
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PRELIMINARY
CY24212
Document History Page
Document Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO
Document Number: 38-07402
REV.
ECN NO. Issue Date
Orig. of
Change
Description of Change
**
117089
09/09/02
CKN
New Data Sheet
*A
120888
12/06/02
CKN
Added -3
*B
123064
02/19/03
CKN
Added -5
*C
345540
See ECN
RGL
Added Pb-free for -5 part
*D
2447126
See ECN
AESA
Updated template. Added Note “Not recommended for new designs.”
Added part number CY24212KSXC-5 in ordering information table.
© Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07402 Rev. *D
Revised April 25, 2008
Page 6 of 6
MediaClock is a trademark of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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