CY24212_05

PRELIMINARY CY24212 MediaClock™ MPEG Clock Generator with VCXO Features • Integrated phase-locked loop (PLL) • Low jitter, high-accuracy outputs • VCXO with analog adjust • 3.3V operation Part Number CY24212-1 CY24212-2 CY24212-3 CY24212-5 Outputs 1 2 2 2 Input Frequency Range 13.5 MHz/27 MHz (selectable) 13.5 MHz/27 MHz (selectable) 27 MHz 27 MHz 27 MHz Two copies of 27 MHz 27 MHz/27.027 MHz (-1 ppm) 27 MHz/27.027 MHz (0 ppm) Benefits Highest-performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Large ±150-ppm range, better linearity Enables application compatibility Output Frequencies Logic Block Diagram XIN XOUT OUTPUT DIVIDERS OSC Q Φ VCO P CLKA (27 MHz) 27 MHz (-2) 27/27.027 MHz (-3) VCXO PLL FSEL VDD VSS Pin Configurations CY24212-1 8-pin SOIC XIN VDD VCXO VSS 1 2 3 4 8 7 6 5 XOUT VSS FSEL CLKA 27 MHz XIN VDD VCXO VSS CY24212-2 8-pin SOIC 1 2 3 4 8 7 6 5 XOUT CLKB 27 MHz FSEL CLKA 27 MHz XIN VDD VCXO VSS CY24212-3,-5 8-pin SOIC 1 2 3 4 8 7 6 5 XOUT CLKB (27/27.027 MHz) FSEL CLKA 27 MHz Table 1. CY24212 (-1, -2) Frequency Select Option FSEL 0 1 Reference 13.5 MHz 27 MHz CLKA/CLKB 27 MHz 27 MHz Table 2. CY24212 (-3, -5) Frequency Select Option FSEL 0 1 Reference 27 MHz 27 MHz CLKA 27 MHz 27 MHz CLKB 27 MHz 27.027 MHz Cypress Semiconductor Corporation Document #: 38-07402 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 6, 2005 PRELIMINARY Pin Description Name XIN VDD VCXO VSS CLKA FSEL (-1,-2) Pin Number 1 2 3 4 5 6 Description Reference Input. Voltage Supply. Input Analog Control for VCXO. Ground. 27-MHz Clock Output. Input Frequency Select, Weak Internal Pull-up. FSEL = 0, XIN = 13.5 MHz FSEL = 1, XIN = 27 MHz Output Frequency Select, Weak Internal Pull-up. FSEL = 0, CLKA = 27 MHz, CLKB = 27 MHz FSEL = 1, CLKA = 27 MHz, CLKB = 27.027 MHz Ground. 27 MHz. 27 MHz/27.027 MHz. Reference Output. CY24212 FSEL (-3,-5) 6 VSS (-1) CLKB (-2) CLKB (-3,-5) XOUT[1] 7 7 7 8 Pullable Crystal Specifications Parameter CRload C0/C1 ESR To Crystal Accuracy TTs Equivalent Series Resistance Operating Temperature Crystal Accuracy Stability over Temperature and Aging 0 35 Name Crystal Load Capacitance Min. Typ. 14 240 50 70 ± 20 ± 50 Ω °C ppm ppm Max. Unit pF Absolute Maximum Conditions Parameter VDD TS TJ Storage Description Supply Voltage Temperature[2] Junction Temperature Digital Inputs Electrostatic Discharge VSS – 0.3 2 Min. –0.5 –65 Max. 7.0 125 125 VDD + 0.3 Unit V °C °C V kV Recommended Operating Conditions Parameter VDD TA CLOAD fREF Description Operating Voltage Ambient Temperature Max. Load Capacitance Reference Frequency 13.5 Min. 3.135 0 Typ. 3.3 Max. 3.465 70 15 27 Unit V °C pF MHz Notes: 1. Float XOUT if XIN is externally driven. 2. Rated for ten years. Document #: 38-07402 Rev. *C Page 2 of 6 PRELIMINARY DC Electrical Specifications Parameter IOH IOL CIN IIH IIL f∆XO VVCXO IDD VIH VIL RUP Name Output High Current Output Low Current Input Capacitance Input High Current Input Low Current VCXO Pullability Range VCXO Input Range Supply Current Input High Voltage Input Low Voltage Pull-up resistor on inputs Sum of Core and Output Current CMOS levels, 70% of VDD CMOS levels, 30% of VDD VDD = 3.14 to 3.47V, measured VIN = 0V 100 0.7 VIH = VDD VIL = 0V – – ±150 0 5 – Description VOH = VDD – 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) Min 12 12 Typ 24 24 CY24212 Max Unit mA mA 7 10 50 VDD 35 0.3 150 pF µA µA ppm V mA VDD VDD kΩ AC Electrical Specifications (VDD = 3.3V) Parameter[3] DC ER EF t9 t10 Name Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. Peak-to-peak period jitter Min 45 0.8 0.8 Typ 50 1.4 1.4 300 3 Max 55 Unit % V/ns V/ns ps ms Test and Measurement Set-up VDDs 0.1 µF DUT Outputs CLOAD GND Note: 3. Not 100% tested. Document #: 38-07402 Rev. *C Page 3 of 6 PRELIMINARY Voltage and Timing Definitions t1 t2 VDD 50% of VDD Clock Output 0V CY24212 Figure 1. Duty Cycle Definition t3 t4 V DD 80% of V DD Clock Output 20% of V DD 0V Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 Ordering Information Ordering Code CY24212SC-1 CY24212SC-1T CY24212SC-2 CY24212SC-2T CY24212SC-3 CY24212SC-3T CY24212SC-5 CY24212SC-5T Lead-free CY24212SXC-5 CY24212SXC-5T S8 S8 8-Pin SOIC 8-Pin SOIC -Tape and Reel Commercial Commercial 3.3V 3.3V Package Name S8 S8 S8 S8 S8 S8 S8 S8 Package Type 8-Pin SOIC 8-Pin SOIC -Tape and Reel 8-Pin SOIC 8-Pin SOIC -Tape and Reel 8-Pin SOIC 8-Pin SOIC -Tape and Reel 8-Pin SOIC 8-Pin SOIC -Tape and Reel Operating Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Document #: 38-07402 Rev. *C Page 4 of 6 PRELIMINARY Package Drawing and Dimensions 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID CY24212 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07402 Rev. *C Page 5 of 6 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page Document Title: CY24212 MediaClock™ MPEG Clock Generator with VCXO Document Number: 38-07402 REV. ** *A *B *C ECN NO. 117089 120888 123064 345540 Issue Date 09/09/02 12/06/02 02/19/03 See ECN Orig. of Change CKN CKN CKN RGL Description of Change New Data Sheet Added -3 Added -5 Added Lead-free for -5 part CY24212 Document #: 38-07402 Rev. *C Page 6 of 6