CY24293ZXC

CY24293 Two Outputs PCI-Express Clock Generator Features ■ ■ ■ ■ ■ ■ ■ ■ Functional Description CY24293 is a two output PCI-Express clock generator device intended for networking applications. The device takes 25 MHz crystal or clock input and provides two pairs of differential outputs at 25 MHz, 100 MHz, 125 MHz, or 200 MHz for HCSL, and 25 MHz or 100 MHz for the LVDS signaling standard. The device incorporates Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction. The spread type and amount can be selected using select pins. 25 MHz Crystal or Clock Input Two sets of Differential PCI-Express Clocks Pin Selectable Output Frequencies Supports HCSL or LVDS Compatible Output Levels Spread Spectrum Capability on all Output Clocks with Pin Selectable Spread Range 16-pin TSSOP Package Operating Voltage 3.3V Commercial and Industrial Operating Temperature Range Logic Block Diagram VDDX VDDO XIN/EXCLKIN (25 MHz) XOUT Clock Buffer/ Crystal Oscillator PCIE0P PCIE0N PLL Clock Synthesizer SS0 SS1 S0 S1 Control Logic PCIE1P PCIE1N I REF OE GNDX GNDO R REF= 475 Ohms 1% Cypress Semiconductor Corporation Document Number: 001-46117 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 02, 2009 [+] Feedback CY24293 Pinouts Figure 1. Pin Diagram - CY24293 16-Pin TSSOP S0 S1 SS0 XIN/EXCLKIN XOUT OE GNDX SS1 1 2 3 4 5 6 7 8 16 15 14 TSSOP 13 12 11 10 9 VDDX PCIE0P PCIE0N GNDO VDDO PCIE1P PCIE1N IREF Table 1. Pin Definitions - CY24293 16-Pin TSSOP Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name S0 S1 SS0 XOUT OE GNDX SS1 IREF PCIE1N PCIE1P VDDO GNDO PCIE0N PCIE0P VDDX Pin Type Input Input Input Output Input Power Input Output Output Output Input Power Output Output Input Description Frequency select pin. Has internal weak pull up. Refer to Table 2. Frequency select pin. Has internal weak pull up. Refer to Table 2. Spread Spectrum Select pin 0. Has internal weak pull up. Refer to Table 3. Crystal or clock input. 25 MHz fundamental mode crystal or clock input. Crystal output. 25 MHz fundamental mode crystal input. Float for clock input. High true output enable pin. When set low, PCI-E outputs are tri-stated. Has internal weak pull up. Ground Spread Spectrum Select pin 1. Has internal weak pull up. Refer to Table 3. Current set for all differential clock drivers. Connect 475Ω resistor to ground. Differential PCI-Express complementary clock output. Tristated when disabled. Differential PCI-Express true clock output. Tristated when disabled. 3.3V Power supply for output driver and analog circuits. Ground Differential PCI-Express complementary clock output. Tristated when disabled. Differential PCI-Express true clock output. Tristated when disabled. 3.3V Power supply for oscillator and digital circuits. XIN/EXCLKIN Input Table 2. Output Selection Table S1 0 0 1 1 S0 0 1 0 1 PCIE0[N,P], PCIE1[N,P] 25 MHz 100 MHz 125 MHz 200 MHz Table 3. Spread Selection Table SS1 0 0 1 1 SS0 0 1 0 1 Spread% No Spread -0.5% -0.75% No Spread Page 2 of 10 Document Number: 001-46117 Rev. *C [+] Feedback CY24293 Application Information Crystal Recommendations CY24293 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24293 to operate at the wrong frequency and violate the ppm specification. For most applications, there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. Table 4. Crystal Recommendations Frequency 25.00 MHz Cut Parallel Load Cap 16 pF Eff Series Rest (max) 30 Ω Drive (max) 1.0 mW Tolerance (max) Stability (max) Aging (max) 30 ppm 10 ppm 5 ppm/yr. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, consider the total capacitance the crystal sees to calculate the appropriate capacitive loading (CL). Figure 2 shows a typical crystal configuration using two trim capacitors. It is important to note that the trim capacitors in series with the crystal are not parallel. It is a common misconception that load capacitors are in parallel with the crystal and must be approximately equal to the load capacitance of the crystal. This is not true. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2: Load capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total capacitance (as seen by the crystal) CLe = 1 ( Ce1 + Cs1 + Ci1 + 1 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned in the previous section, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1, Ce2) must be calculated to provide equal capacitive loading on both sides. Figure 2. Crystal Loading Example Clock Chip Current Source (Iref) Reference Resistor If the board target trace impedance (Z) is 50Ω, then for RREF = 475Ω (1%), provides IREF of 2.32 mA. The output current (IOH) is equal to 6*IREF. Output Termination The PCI-Express differential clock outputs of the CY24293 are open source drivers and require an external series resistor and a resistor to ground. These resistor values and their allowable locations are explained in the section PCI-Express Layout Guidelines on page 4. The CY24293 can also be configured for LVDS compatible voltage levels. Refer to the section LVDS Compatible Layout Guidelines on page 5. Ci1 Ci2 Pin 3 to 6p Cs1 X1 X2 Cs2 Trace 2.8 pF XTAL Ce1 Ce2 Trim 26 pF Document Number: 001-46117 Rev. *C Page 3 of 10 [+] Feedback CY24293 PCB Layout Recommendations For optimum device performance and the lowest phase noise, the following guidelines must be observed: 1. Each 0.01 µF decoupling capacitor must be mounted on the component side of the board as close to the VDD pin as possible. 2. No vias must be used between the decoupling capacitor and the VDD pin. 3. The PCB trace to the VDD pin and the ground via must be kept as short as possible. Distance of the ferrite bead and bulk decoupling from the device is less critical. 4. An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). Other signal traces must be routed away from the CY24293. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. Decoupling Capacitors The decoupling capacitors of 0.01 µF must be connected between VDD and GND as close to the device as possible. Do not share ground vias between components. Route power from the power source through the capacitor pad and then into the CY24293 pin. PCI-Express Layout Guidelines HCSL Compatible Layout Guidelines Table 5. Common Recommendations for Differential Routing Differential Routing[1] L1 length, route as non-coupled 50Ω trace L2 length, route as non-coupled 50Ω trace L3 length, route as non-coupled 50Ω trace RS RT Table 6. Differential Routing for PCI-Express Load or Connector Differential Routing[1] L4 length, route as coupled microstrip 100Ω differential trace L4 length, route as coupled stripline 100Ω differential trace Dimension or Value 2 to 32 1.8 to 30 Unit inch inch Dimension or Value 0.5 max 0.2 max 0.2 max 33 49.9 Unit inch inch inch Ω Ω Figure 3. PCI-Express Device Routing Rs L1 RS L1 L2 L4 L2 L4 RT Output Buffer L3 L3 RT PCI Express Load or Connector Note 1. Refer to Figure 3. Document Number: 001-46117 Rev. *C Page 4 of 10 [+] Feedback CY24293 LVDS Compatible Layout Guidelines Table 7. Common Recommendations for Differential Routing Differential Routing[2] L1 length, route as noncoupled 50Ω trace L2 length, route as noncoupled 50Ω trace L3 length, route as noncoupled 50Ω trace RP RQ RS RT Table 8. LVDS Device Differential Routing Differential Routing[2] L4 length, route as coupled microstrip 100Ω differential trace L4 length, route as coupled stripline 100Ω differential trace Dimension or Value 2 to 32 1.8 to 30 Unit inch inch Dimension or Value 0.5 max 0.2 max 0.2 max 100 150 33 49.9 Unit inch inch inch Ω Ω Ω Ω Figure 4. LVDS Device Routing Rs L1 Rs L1 L2 L4 RQ L2 L4 RP RT Output Buffer L3 L3 RT LVDS Device Input Note 2. Refer to Figure 4. Document Number: 001-46117 Rev. *C Page 5 of 10 [+] Feedback CY24293 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 9. Absolute Maximum Ratings Parameter VDD VIN TS TJ ESDHBM UL-94 MSL Input voltage Temperature, Storage Temperature, Junction ESD Protection (Human Body Model) Flammability rating Moisture sensitivity level Description Supply voltage Relative to VSS Non Functional Non Functional JEDEC EIA/JESD22-A114-E Condition Min –0.5 –0.5 –65 –65 2000 3 Max 4.6 VDD+0.5 +150 +150 – Unit V V °C °C V V-0 at 1/8 in. Recommended Operation Conditions Parameter VDD TAC TAI tPU Description Supply voltage Commercial ambient temperature Industrial ambient temperature Power up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Min 3.0 0 –40 0.05 Typ – – – – Max 3.6 +70 +85 500 Unit V °C °C ms DC Electrical Characteristics Unless otherwise stated, VDD = 3.3V ±0.3V, ambient temperature = -40°C to +85°C Industrial, 0°C to +70°C Commercial Parameter[3] VIL VIH VOL VOH IDD IDDOD CIN RPU Description Input low voltage Input high voltage Output low voltage of PCIE0[P/N], PCIE1[P/N] Output high voltage of PCIE0[P/N], PCIE1[P/N] Operating supply current Output disabled current Input capacitance Pull up resistance HCSL termination (RS = 33Ω, RT = 49.9Ω) HCSL termination (RS = 33Ω, RT = 49.9Ω) No load, OE = 1 OE = 0 All input pins S0, S1, SS0, SS1, OE Condition Min -0.3 2.0 -0.2 0.65 – – – – Typ – – 0 0.71 45 – 5 70k Max 0.8 VDD+0.3 0.05 0.85 60 50 – – Unit V V V V mA mA pF Ω Note 3. Parameters are guaranteed by design and characterization. Not 100% tested in production Document Number: 001-46117 Rev. *C Page 6 of 10 [+] Feedback CY24293 , AC Electrical Characteristics Unless otherwise stated: VDD = 3.3V ±0.3V, ambient temperature = -40°C to +85°C Industrial, 0°C to +70°C Commercial, Outputs HCSL terminated. Parameter[3] FIN FOUT FERR TCCJ SPMOD TDC TOEH TOEL TLOCK TR TF DTR DTF TOSKEW VCROSS VXdelta Description Input clock frequency (crystal or external clock) Output frequency Frequency synthesis error Cycle-to-cycle jitter Output clock duty [4] Condition Min – Typ 25 – – 0 – 32 50 – – 1 – – – – – 0.35 – Max – 200 100 – 75 – 55 200 200 2 700 700 125 125 50 0.55 140 Unit MHz MHz MHz ppm ps kHz % ns ns ms ps ps ps ps ps V mV HCSL Termination LVDS Termination – – – – – 45 Spread modulation frequency cycle[4,6] OE going high to differential outputs becoming valid OE going low to differential outputs becoming invalid Measured from 90% of the applied power supply level Measured from 0.175V to 0.525V Measured from 0.525V to 0.175V For a given frequency, Max(TR) - Min (TR) For a given frequency, Max(TF) - Min (TF) Measured at VCROSS point Output enable time Output disable time Clock stabilization from power up Output rise time[4,5] Output fall time[4,5] Rise time variation[4,5] Fall time variation[4,5] Output skew[6] Absolute crossing point voltage[6,7] Variation of VCROSS over all clock edges[6,8] – – – 130 130 – – – 0.25 – Test and Measurement Setup Figure 5. Test Load Configuration for Differential Output Signals 33 Ohm PCIEP CLoad 33 Ohm PCIEN CLoad 475 Ohm 50 Ohm 50 Ohm Notes 4. Measured with Cload = 4 pF max. (scope probe + trace load) 5. Measurement taken from a differential waveform. 6. Measured at crossing point where the instantaneous voltage value of the rising edge of PCIEP equals the falling edge of PCIEN. 7. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing points for this measurement. 8. Refers to the difference between the PCIEP rising edge VCROSS average value and the PCIEN rising edge VCROSS average value. Document Number: 001-46117 Rev. *C Page 7 of 10 [+] Feedback CY24293 Ordering Information Part Number Pb-free CY24293ZXC CY24293ZXCT CY24293ZXI CY24293ZXIT 16-pin TSSOP 16-pin TSSOP tape & reel 16-pin TSSOP 16-pin TSSOP tape & reel Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, -40°C to 85°C Industrial, -40°C to 85°C Type Production Flow Package Dimensions Figure 6. 16-Pin TSSOP 4.40 mm Body Package PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.05gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85091 *A Document Number: 001-46117 Rev. *C Page 8 of 10 [+] Feedback CY24293 Document History Page Document Title: CY24293 Two Outputs PCI-Express Clock Generator Document Number: 001-46117 REV. ** *A ECN NO. Orig. of Change Submission Date 2490167 2507681 PYG/DPF/AESA DPF/AESA See ECN New Data Sheet Description of Change 05/23/2008 Added Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. Added Note 2 for Duty cycle spec in the AC Elect. Characteristics. Added HCSL termination in Condition for VOL, VOH DC Elect. Char. Added VXdelta value of 140 mV in the Differential 100 MHz HCSL output. Changed Cload from 2 pF to 4 pF in Note 2. Added internal weak Pull ups for S0, S1, SS0, SS1 and OE pins. Updated TOEH and TOEL to 200 ns (max.). Updated data sheet template *B 2621901 CXQ/AESA 12/19/2008 Updated IDD spec in DC Electrical Characteristics. Added max spec for IDDOD DC Electrical Characteristics. Added RPU in DC Electrical Characteristics. Replaced TRFVAR with DTR and DTF in AC Electrical Characteristics. Added definitions for rise and fall time variation, crossing point variation in AC Electrical Characteristics. Reduced cycle-to-cycle jitter spec to 75ps in AC Electrical Characteristics. 04/03/2009 Removed “Preliminary” from datasheet title and headings Added “max” to crystal ESR spec. Changed “LVDS Down Device” to “LVDS Device” in Table 8 and Figure 4. *C 2683343 CXQ/PYRS Document Number: 001-46117 Rev. *C Page 9 of 10 [+] Feedback CY24293 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. 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Document Number: 001-46117 Rev. *C Revised April 02, 2009 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback