CY24713KSXCT

CY24713 Set-top Box Clock Generator with VCXO Features Benefits ■ Integrated phase-locked loop (PLL) ■ High-performance PLL tailored for Set Top Box applications ■ Low-jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs ■ VCXO with analog adjust ■ Large ±150-ppm range, better linearity ■ 3.3V Operation ■ Meet industry standard voltage platforms ■ 8-pin SOIC ■ Industry standard packaging saves on board space Part Number Outputs Input Frequency Range Output Frequencies CY24713 3 27-MHz pullable crystal input per Cypress specification 4.9152 MHz, 13.5 MHz, 27 MHz Logic Block Diagram Pin Configuration Figure 1. CY24713, 8-Pin SOIC Table 1. Pin Definition Name Number Description XIN 1 Reference Crystal Input VDD 2 3.3V Voltage Supply VCXO 3 Input Analog Control for VCXO VSS 4 Ground CLK_B 5 13.5-MHz Clock Output CLK_A 6 4.9152-MHz Clock Output CLK_C 7 27-MHz Clock Output 8 Reference Crystal Output XOUT [1] Note 1. Float XOUT if XIN is externally driven. Cypress Semiconductor Corporation Document #: 38-07396 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 26, 2010 [+] Feedback CY24713 Absolute Maximum Conditions Parameter VDD Description Supply Voltage [2] Min Max Unit –0.5 7.0 V TS Storage Temperature –65 125 °C TJ Junction Temperature – 125 °C Digital Inputs VSS – 0.3 VDD + 0.3 V Digital Outputs referred to VDD VSS – 0.3 VDD + 0.3 V – 2000 V –0.5 7.0 V Electrostatic Discharge Analog Input Pullable Crystal Specifications Parameter Description Condition Min Typ. Max Unit – 27 – MHz – 14 – pF – – 25 Ω FNOM Nominal crystal frequency CLNOM Nominal load capacitance R1 Equivalent series resistance (ESR) R3/R1 Ratio of third overtone mode ESR to fundamen- Ratio used because typical R1 tal mode ESR values are much less than the maximum spec. 3 – – DL Crystal drive level No external series resistor assumed – 0.5 2.0 mW F3SEPHI Third overtone separation from 3*FNOM High side 300 – – ppm F3SEPLO Third overtone separation from 3*FNOM Low side – – –150 ppm C0 Crystal shunt capacitance – – 7 pF C0/C1 Ratio of shunt to motional capacitance 180 – 250 C1 Crystal motional capacitance 14.4 18 21.6 pF Min Typ. Max Unit 3.135 3.3 3.465 V 0 – 70 °C Parallel resonance, fundamental mode, AT cut Fundamental mode Recommended Operating Conditions Parameter Description VDD Operating Voltage TA Ambient Temperature CLOAD Max. Load Capacitance tPU Power up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) – – 15 pF 0.05 – 500 ms DC Electrical Characteristics Description Conditions Min Typ. Max Unit IOH Parameter Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 – mA VOL = 0.5, VDD = 3.3V 12 24 – mA – – 7 pF IOL Output Low Current CIN Input Capacitance IIZ Input Leakage Current – 5 – μA fΔXO VCXO pullability range ±150 – – ppm VVCXO VCXO input range 0 – VDD V IVDD Supply Current – 25 30 mA Note 2. Rated for 10 years Document #: 38-07396 Rev. *B Page 2 of 5 [+] Feedback CY24713 AC Electrical Characteristics (VDD = 3.3V) Parameter[3] Description Conditions Min Typ. Max Unit DC Output Duty Cycle Duty Cycle is defined in Figure 3 50% of VDD 45 50 55 % ER0 Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF Figure 4. 0.8 1.4 – V/ns EF1 Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF Figure 4. 0.8 1.4 – V/ns t9 Clock Jitter Peak-Peak period jitter maximum absolute jitter – 200 250 ps t10 PLL Lock Time – – 3 ms Figure 2. Test Circuit V DD CLK out 0.1 μF C LOAD OUTPUTS GND Figure 3. Duty Cycle Definition; DC = t2/t1 t1 t2 CLK 50% 50% Figure 4. Rise and Fall Time Definitions: ER = 0.6 x VDD/t3, EF = 0.6 x VDD/t4 t3 t4 80% CLK 20% Note 3. Not 100% tested Document #: 38-07396 Rev. *B Page 3 of 5 [+] Feedback CY24713 Ordering Information Ordering Code Package Type Operating Range Operating Voltage CY24713KSXC 8-pin SOIC Commercial 3.3V CY24713KSXCT 8-pin SOIC-Tape and Reel Commercial 3.3V Pb-free Package Diagram Figure 5. 8-Pin (150-Mil) SOIC S8 51-85066 *D Document #: 38-07396 Rev. *B Page 4 of 5 [+] Feedback CY24713 Document History Page Document Title: CY24713 Set-top Box Clock Generator with VCXO Document Number: 38-07396 Rev. ECN No. Orig. of Change Submission Date ** 333175 RGL See ECN New Data Sheet *A 2440886 AESA See ECN Updated template. Added Note “Not recommended for new designs.” Added part number CY24713KSXC, and CY24713KSXCT in ordering information table. Replaced Lead-Free with Pb-Free. *B 2899683 CXQ 03/26/10 Description of Change Removed inactive parts from ordering information table Updated package diagram Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2005-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07396 Rev. *B Revised March 26, 2010 Page 5 of 5 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback