CY25200
Programmable Spread Spectrum
Clock Generator for EMI Reduction
Features
Description
■
Wide Operating Output (SSCLK) Frequency Range
❐ 3 to 200 MHz
■
Programmable Spread Spectrum with Nominal 31.5 kHz
modulation Frequency
The CY25200 is a programmable clock generator with spread
spectrum capability. Spread spectrum modulates the output
clock frequency over a small range, spreading the energy and
reducing the energy peak. This is a powerful technique to reduce
EMI in a variety of applications.
■
Center Spread: ±0.25% to ±2.5%
■
Down Spread: –0.5% to –5.0%
■
Input Frequency Range
❐ External crystal: 8 to 30 MHz fundamental crystals
❐ External reference: 8 to 166 MHz clock
■
Integrated Phase-Locked Loop (PLL)
■
Programmable Crystal Load Capacitor Tuning Array
■
Low Cycle-to-Cycle Jitter
■
3.3V Operation with 2.5V Output Clock Drive Option
■
Spread Spectrum On and Off Function
■
Power Down or Output Enable Function
■
Output Frequency Select Option
■
Field-Programmable
■
Package: 16 Pin TSSOP
It uses either an external reference clock or a crystal for an input.
It also uses a PLL to generate a spread spectrum output clock
that can be a different frequency than the input. Up to six output
clocks are available and up to two of them can be REFCLKs
(copies of the input clock, without spread).
The CY25200 is highly configurable. Programmable variables
include the input and output frequencies, spread percentage,
center spread or down spread, and control pin functions. The
oscillator pin capacitance can also be programmed to match the
load capacitance requirement (CL)of the crystal, eliminating the
need for external capacitors.
Available features include Output Enable, Power Down, Spread
On/Off, Frequency Select, and the option to power some output
clocks at 2.5V.
Cypress’ web-based CyberClocks Online software is used to
configure the device. Programmability enables fast prototyping,
which is particularly useful when doing EMC testing and determining the optimal spread settings.
Logic Block Diagram
7
Divider
Bank 1
XIN/CLKIN 1
OSC.
Q
CXOUT
8 SSCLK2
Output
Select
Matrix
Φ
VCO
XOUT 16
P
CXIN
SSCLK1
9
SSCLK3
12 SSCLK4
Divider
Bank 2
PLL
14 SSCLK5/REFOUT/CP2
15 SSCLK6/REFOUT/CP3
2
VDD
Cypress Semiconductor Corporation
Document #: 38-07633 Rev. *F
•
3
AVDD
5
AVSS
13
VSS
11
VDDL
198 Champion Court
6
4
CP0
VSSL
•
10
CP1
San Jose, CA 95134-1709
•
408-943-2600
Revised September 01, 2009
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CY25200
Pin Configuration
Figure 1. Pin Diagram
General Description
The CY25200 is a Spread Spectrum Clock Generator (SSCG) IC
used to reduce Electro Magnetic Interference (EMI) found in
today’s high speed digital electronic systems.
The device uses a Cypress proprietary Phase-Locked Loop
(PLL) and Spread Spectrum Clock (SSC) technology to
synthesize and modulate the frequency of the input clock. By
frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are reduced. This reduction in
radiated energy significantly reduces the cost of complying with
regulatory agency requirements (EMC) and improves time to
market, without degrading system performance.
The CY25200 uses a factory and field-programmable configuration memory array to synthesize output frequency, spread %,
crystal load capacitor, clock control pins, PD#, and OE options.
The spread % is factory and field-programmed to either center
spread or down spread with various spread percentages. The
range for center spread is from ±0.25% to ±2.50%. The range for
down spread is from –0.5% to –5.0%. Contact the factory for
smaller or larger spread % amounts, if required.
The input to the CY25200 is either a crystal or a clock signal. The
input frequency range for crystals is 8 to 30 MHz and for clock
signals is 8 to 166 MHz.
The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The
frequency modulated SSCLK outputs are programmed from 3 to
200 MHz.
The CY25200 products are available in a 16-pin TSSOP
package with a commercial operating temperature range of 0 to
70°C.
Table 1. Pin Summary
Name
XIN
XOUT
VDD
AVDD
VSS
AVSS
VDDL
VSSL
SSCLK1
SSCLK2
SSCLK3
SSCLK4
SSCLK5/REFOUT/CP2
Pin Number
1
16
2
3
13
5
11
6
7
8
9
12
14
Description
Crystal input or Reference Clock input
Crystal output. Leave this pin floating if external clock is used
3.3V power supply for digital logic and SSCLK5 and 6 clock outputs
3.3V analog–PLL power supply
Ground
Analog ground
2.5V or 3.3V power supply for SSCLK1/2/3/4 clock outputs
VDDL power supply ground
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock output at VDDL level (2.5V or 3.3V)
Programmable spread spectrum clock or buffered reference output at VDD
level (3.3V) or control pin, CP2
SSCLK6/REFOUT/CP3
15
CP0[1]
CP1[1]
4
10
Programmable spread spectrum clock or buffered reference output at VDD
level (3.3V) or control pin, CP3
Control pin 0
Control pin 1
Note
1. Pins are programmed to be any of the following control signals: OE: Output Enable, OE = 1, all the SSCLK outputs are enabled; PD#: Power down, PD# = 0, all the
SSCLK outputs are three-stated and the part enters a low power state; SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1, Spread Signal),
CLKSEL: SSCLK Output Frequency Select.See Control Pins (CP0, CP1, CP2 and CP3) for control pins programming options.
Document #: 38-07633 Rev. *F
Page 2 of 12
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CY25200
Table 2. Fixed Function Pins
Pin Function
Output Clock Frequency
Input Frequency
CXIN and CXOUT
Spread Percent
Modulation
Frequency
Pin Name
SSCLK[1:6]
XIN and XOUT
XIN and XOUT
SSCLK[1:6]
SSCLK[1:6]
Pin#
7, 8, 9, 12, 14, 15
1 and 16
1 and 16
7,8,9,12,14,15
7,8,9,12,14,15
Units
MHz
MHz
pF
% and Center- or
Down-spread
kHz
Program Value
CLKSEL = 0
USER SPECIFIED
USER SPECIFIED
USER SPECIFIED
Program Value
CLKSEL = 1
USER SPECIFIED
USER SPECIFIED USER SPECIFIED
Table 3. Multi-Function Pins
Pin
Function
Output Clock/REFOUT/OE/SSON/CLKSEL
OE/PD#/SSON/CLKSEL
Pin Name
SSCLK5/REFOUT/CP2
SSCLK6/REFOUT/CP3
CP0
CP1
Pin#
14
15
4
10
Units
Function
Function
Function
Function
USER SPECIFIED
USER SPECIFIED
USER SPECIFIED
USER SPECIFIED
Programming Description
Field-Programmable CY25200
The CY25200 is programmed at the package level, and must be
programmed prior to installation on a circuit board. Field
programmable devices are denoted by an “F” in the ordering
code, and are blank when shipped. The CY25200 is Flash
technology based, which allows it to be reprogrammed up to 100
times. This allows for fast and easy design changes and product
updates, and eliminates issues with old and out of date inventory.
Samples and small prototype quantities are programmed on the
CY3672 programmer with the CY3695 socket adapter.
standard JEDEC file used for programming the CY25200. CyberClocks Online is available at www.cyberclocksonline.com
website.
Factory-Programmed CY25200
Factory programming by Cypress is available for high volume
orders. All requests must be submitted to the local Cypress Field
Application Engineer (FAE) or sales representative. After the
request is processed, you will receive a new part number,
samples, and data sheet with the programmed values. This part
number is used for additional sample requests and production
orders.
CyberClocks™ Online Software
CyberClocks™ Online Software is a web based software application that allows the user to custom configure the CY25200. All
the parameters in Table 2 and Table 3 are entered as variables
into the software. CyberClocks Online outputs an industry
Document #: 38-07633 Rev. *F
Page 3 of 12
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CY25200
Product Functions
CLKSEL
Control Pins (CP0, CP1, CP2 and CP3)
Four control signals are available through programming of pins
4, 10, 14, and 15.
CP0 (pin 4) and CP1 (pin10) are specifically designed to function
as control pins. However, pins 14 (SSCLK5/REFOUT/CP2) and
15 (SSCLK6/REFOUT/CP3) are multi-functional and can be
programmed to be either a control signal or an output clock
(SSCLK or REFOUT). All of the control pins, CP0, CP1, CP2,
and CP3 are programmable to one of the following functions:
The CLKSEL control pin enables you to select between two
different SSCLK output frequencies. These must be related
frequencies that are derived off of a common PLL frequency.
Specifically, CLKSEL does not change the PLL frequency. It only
changes the output divider. For instance, 33.333 MHz and
66.666 MHz are both derived from a PLL frequency of 400 MHz,
by dividing it down by 12 and 6 respectively. Table 4 shows an
example of how this is implemented. The PLL frequency range
is 100 to 400 MHz. The two output dividers in the CY25200 can
be any integer between 2 and 130, providing two different but
related frequencies as explained above.
■
OE (Output Enable): if OE = 1, all SSCLK and REFOUT outputs
are enabled.
■
SSON (Spread spectrum control): if SSON = 1, spread is on;
if SSON = 0, spread is off.
Table 4 and Figure 3 show an example configuration using the
frequencies just described. In this example, the configurable pins
SSCLK5 (pin 14) and SSCLK6 (pin 15) are used as output
clocks.
■
CLKSEL (Clock select): frequency select for all SSCLK outputs.
Input Frequency (XIN, Pin 1 and XOUT, Pin 16)
■
PD# (Power Down; active low): if PD# = 0, all the outputs are
three-stated and the part enters a low power state.
The input to the CY25200 is a crystal or a clock. The input frequency range for crystals is 8 to 30 MHz, and for clock signal is
8 to 166 MHz.
Note that the PD# function is available only on CP0 or CP1; it is
not available on CP2 or CP3.
Example
Here is an example with three control pins:
■
CLKIN = 33 MHz
■
SSCLK1/2/3/4 = 100 MHz with ±1% spread
■
SSCLK 5 = REFOUT(33 MHz)
■
CP0 (Pin 4) = PD#
■
CP1 (Pin 10) = OE
■
CP3 (pin 15) = SSON
CXIN and CXOUT (Pin 1 and Pin 16)
The CY25200 has internal load capacitors at pin 1 (CXIN) and pin
16 (CXOUT). CXIN always equals CXOUT, and they are programmable from 12 pF to 60 pF, in 0.5 pF increments. This feature
eliminates the need for external crystal load capacitors.
The following formula is used to calculate the value of CXIN and
CXOUT for matching the crystal load (CL):
CXIN = CXOUT = 2CL – CP
Where CL is the crystal load capacitor as specified by the crystal
manufacturer and CP is the parasitic PCB capacitance on each
node of the crystal.
The pinout for the above example is shown in Figure 2.
Figure 2. Example Pin Diagram
33.0MHz
VDD
1
16
NC
2
15
AVDD
3
14
PD#
4
13
SSON
REFOUT(33.0MHz)
VSS
AVSS
5
12
100MHz
VSSL
6
11
VDDL
100MHz
7
10
OE
100MHz
8
9
Document #: 38-07633 Rev. *F
100MHz
For example, if a crystal with CL of 16 pF is used, and CP is 2 pF,
CXIN and CXOUT is calculated as:
CXIN = CXOUT = (2 x 16) – 2 = 30 pF.
If using a driven reference clock, set CXIN and CXOUT to the minimum value 12 pF, connect the reference to XIN/CLKIN, and
leave XOUT unconnected.
Output Frequency (SSCLK1 through SSCLK6
Outputs)
All the SSCLK outputs are produced by synthesizing the input
reference frequency using a PLL and modulating the VCO
frequency. SSCLK[1:4] are fixed function output clocks (SSCLK).
SSCLK5 and SSCLK6 are also programmable to function the
same as SSCLK[1:4], or as buffered copies of the input reference
(REFOUT), or as control pin as discussed in Control Pins (CP0,
CP1, CP2 and CP3). To use the 2.5V output drive option on
SSCLK[1:4], VDDL must be connected to a 2.5V power supply
(SSCLK[1:4] outputs are powered by VDDL). When using the
2.5V output drive option, the maximum output frequency on
SSCLK[1:4] is 166 MHz.
Page 4 of 12
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CY25200
Spread Percentage (SSCLK1 to SSCLK6 Outputs)
Modulation Frequency
The SSCLK frequency is programmed to a percentage value
from ±0.25% to ±2.5% for center spread and from –0.5% to
–5.0% down spread. The granularity is 0.25%.
The default modulation frequency is 31.5 kHz. Other modulation
frequencies available via the configuration software are 30.1 kHz
and 32.9 kHz.
Table 4. Using Clock Select, CLKSEL Control Pin
Input Frequency
(MHz)
CLKSEL
(Pin 4)
SSCLK1
(Pin 7)
SSCLK2
(Pin 8)
SSCLK3
(Pin 9)
SSCLK4
(Pin 12)
REFOUT
(Pin 14)
REFOUT
(Pin 15)
14.318
CLKSEL = 0
33.33
33.33
33.33
33.33
14.318
14.318
CLKSEL = 1
66.66
66.66
66.66
66.66
14.318
14.318
Figure 3. Using Clock Select, CLKSEL Control Pin Configuration Pinout
Document #: 38-07633 Rev. *F
14.318 MHz
1
16
XOUT
VDD
2
15
REFOUT(14.318 MHz)
AVDD
3
14
REFOUT(14.318MHz)
CLKSEL
4
13
VSS
AVSS
5
12
33.33/66.66 MHz
VSSL
6
11
VDDL
33.33/66.66 MHz
7
10
SSON
33.33/66.66 MHz
8
9
33.33/66.66 MHz
Page 5 of 12
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CY25200
Switching Waveforms
Figure 4. Duty Cycle Timing (DC = t1A/t1B)
Figure 5. Output Rise and Fall Time (SSCLK and REFCLK)
VDD
OUTPUT
0V
Tr
Tf
Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3)
Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4)
Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
Figure 6. Power Down and Power Up Timing
POWER
DOWN
VDD
0V
VIH
VIL
tPU
High Impedance
SSCLK
(Asynchronous)
tSTP
Figure 7. Output Enable and Disable Timing
OUTPUT
ENABLE
VDD
0V
VIH
VIL
High Impedance
SSCLK
(Asynchronous
TOE2
)
TOE1
a
Document #: 38-07633 Rev. *F
Page 6 of 12
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CY25200
Informational Graphs
The informational graphs are meant to convey the typical performance levels. No performance specifications is implied or guaranteed.
172.5
171.5
68.5
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= -4%
170.5
169.5
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= -4%
68
67.5
168.5
167.5
166.5
67
66.5
Fnominal
165.5
164.5
163.5
162.5
Fnominal
66
65.5
65
64.5
64
161.5
63.5
160.5
159.5
0
0
20
169.5
169
168.5
168
167.5
167
166.5
166
165.5
165
164.5
164
163.5
163
40
60
80
100
120
Time (us)
140
160
180
20
40
60
80
200
Spread Spectrum Profile: Fnom=166MHz,
Fmod=30kHz, Spread%= +/-1%
67.5
100
120
Time (us)
140
160
180
200
Spread Spectrum Profile: Fnom=66MHz,
Fmod=30kHz, Spread%= +/-1%
67
66.5
Fnominal
Fnominal
66
65.5
65
64.5
162.5
0
0
20
40
60
80
100 120
Time (us)
Document #: 38-07633 Rev. *F
140
160
180
200
20
40
60
80
100 120
Time (us)
140
160
180
200
Page 7 of 12
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CY25200
Absolute Maximum Rating
Supply Voltage (VDD)....................................... –0.5 to +7.0V
Data Retention at Tj = 125°C ................................> 10 years
DC Input Voltage ......................................–0.5V to VDD + 0.5
Package Power Dissipation...................................... 350 mW
Storage Temperature (non-condensing) ..... –55°C to +125°C
Static Discharge Voltage.......................................... > 2000V
(per MIL-STD-883, Method 3015)
Junction Temperature ................................ –40°C to +125°C
Recommended Crystal Specifications
Parameter
FNOM
Description
Nominal Crystal Frequency
CLNOM
R1
Nominal Load Capacitance
Equivalent Series Resistance
(ESR)
Ratio of Third Overtone Mode
Ratio used because typical R1 values
ESR to Fundamental Mode ESR are much less than the maximum
specification
Crystal Drive Level
No external series resistor assumed
R3/R1
DL
Comments
Parallel resonance, fundamental
mode, AT cut
Internal load caps
Fundamental mode
Min
8
Typ.
Max
30
Unit
MHz
30
25
pF
Ω
0.5
2
mW
Min
3.135
3.135
2.375
0
–
–
3
3
8
8
8
0.05
Typ
3.3
3.3
2.5
–
–
–
–
–
–
–
–
–
Max
3.465
3.465
2.625
70
15
15
200
166
166
166
30
500
Unit
V
V
V
°C
pF
pF
MHz
MHz
MHz
MHz
MHz
ms
Min
12
12
8
8
0.7
0
–
–
–
–
–
Typ.
24
24
16
16
–
–
–
–
–
–
–
Max
–
–
–
–
1.0
0.3
33
20
26
50
10
Unit
mA
mA
mA
mA
VDD
VDD
mA
mA
mA
μA
μA
6
3
Recommended Operating Conditions
Parameter
VDD
VDDLHI
VDDLLO
TAC
CLOAD
CLOAD
FSSCLK-HighVoltage
FSSCLK-LowVoltage
REFOUT
fREF1
fREF2
tPU
Description
Operating Voltage
Operating Voltage
Operating Voltage
Ambient Commercial Temp
Maximum Load Capacitance VDD/VDDL = 3.3V
Maximum Load Capacitance VDDL = 2.5V
SSCLK1/2/3/4/5/6 when VDD = AVDD = VDDL = 3.3 V
SSCLK1/2/3/4 when VDD = AVDD = 3.3.V and VDDL = 2.5V
REFOUT when VDD = AVDD = 3.3.V and VDDL = 3.3V or 2.5V
Clock Input
Crystal Input
Power up time for all VDDs to reach minimum specified voltage (power
ramps must be monotonic)
DC Electrical Specifications
Parameter[2]
IOH3.3
IOL3.3
IOH2.5
IOL2.5
VIH
VIL
IVDD[3]
IVDDL2.5[3]
IVDDL3.3[3]
IDDS
IOHZ
IOLZ
Name
Output High Current
Output Low Current
Output High Current
Output Low Current
Input High Voltage
Input Low Voltage
Supply Current
Supply Current
Supply Current
Power Down Current
Output Leakage
Description
VOH = VDD – 0.5V, VDD/VDDL = 3.3V
VOL = 0.5V, VDD/VDDL = 3.3V
VOH = VDDL – 0.5V, VDDL = 2.5V
VOL = 0.5V, VDDL = 2.5V
CMOS levels, 70% of VDD
CMOS levels, 30% of VDD
AVDD/VDD Current
VDDL Current (VDDL = 2.625V)
VDDL Current (VDDL = 3.465V)
VDD = VDDL = AVDD = 3.465V
VDD = VDDL = AVDD = 3.465V
Notes
2. Not 100% tested, guaranteed by design.
3. IVDD currents specified for SSCLK1/2/3/4/5/6 = 33.33 MHz with CLKIN = 14.318 MHz and 15 pF on all the output clocks.
Document #: 38-07633 Rev. *F
Page 8 of 12
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CY25200
AC Electrical Specifications
Parameter
DC
Description
Condition
Min
Typ
Max
Unit
Output Duty Cycle
SSCLK, Measured at VDD/2
45
50
55
%
Output Duty Cycle
REFCLK, Measured at VDD/2
Duty Cycle of CLKIN = 50%.
40
50
60
%
SR1
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 3.3V
0.6
–
2.0
V/ns
SR2
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 ≥ 100 MHz, VDD = VDDL = 3.3V
0.8
–
3.5
V/ns
SR3
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 2.5V
0.5
–
2.2
V/ns
SR4
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 ≥ 100 MHz, VDD = VDDL = 2.5V
0.6
–
3.0
V/ns
SR5
Rising/Falling Edge Slew Rate SSCLK5/6 < 100 MHz, VDD = VDDL = 3.3V
0.6
–
1.9
V/ns
SR6
Rising/Falling Edge Slew Rate SSCLK5/6 ≥ 100 MHz, VDD = VDDL = 3.3V
1.0
–
2.9
V/ns
TCCJ1
Cycle-to-Cycle Jitter
SSCLK1/2/3/4
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
110
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
170
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
140
ps
CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
290
ps
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
100
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
120
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
180
ps
CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
–
–
180
ps
CLKIN = SSCLK1/2/3/4 = 166 MHz, ±2% spread and
SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
110
ps
CLKIN = SSCLK1/2/3/4 = 66.66 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
170
ps
CLKIN = SSCLK1/2/3/4 = 33.33 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
190
ps
CLKIN = SSCLK1/2/3/4 = 14.318 MHz, ±2% spread
and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
–
–
330
ps
TCCJ2
TCCJ3
Cycle-to-Cycle Jitter
SSCLK5/6=REFOUT
Cycle-to-Cycle Jitter
SSCLK1/2/3/4
TSTP
Power Down Time
Time from falling edge on PD# to stopped outputs
(Asynchronous)
–
150
300
ns
TOE1
Output Disable Time
Time from falling edge on OE to stopped outputs
(Asynchronous)
–
150
300
ns
TOE2
Output Enable Time
Time from rising edge on OE to outputs at a valid
frequency (Asynchronous)
–
150
300
ns
FMOD
Spread Spectrum Modulation
Frequency
SSCLK1/2/3/4/5/6
30.0
31.5
33.0
kHz
TPU1
Power Up Time,
Crystal is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
–
3
5
ms
TPU2
Power Up Time,
Reference clock is used
Time from rising edge on PD# to outputs at valid
frequency (Asynchronous)
–
2
3
ms
TSKEW[4]
Clock Skew
Output to output skew between related clock
outputs. Measured at VDD/2.
–
–
250
ps
Note
4. Skew and phase alignment is guaranteed within all SSCLK outputs and within both REFOUT outputs. All SSCLK outputs are related, and all REOUT outputs are
related, but SSCLK and REFOUT outputs are not related to each other.
Document #: 38-07633 Rev. *F
Page 9 of 12
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CY25200
Ordering Information
Ordering Code[5]
[6]
Package Type
Programming Operating Temperature Range
CY25200-ZXCxxxw
16-Pin TSSOP (Pb-free)
Factory
Commercial, 0 to 70°C
CY25200-ZXCxxxwT[6]
16-Pin TSSOP – Tape and Reel (Pb-free)
Factory
Commercial, 0 to 70°C
CY25200FZXC
[6]
16-Pin TSSOP (Pb-free)
Field
Commercial, 0 to 70°C
CY25200K-ZXCxxxw
16-Pin TSSOP (Pb-free)
Factory
Commercial, 0 to 70°C
CY25200K-ZXCxxxwT
16-Pin TSSOP – Tape and Reel (Pb-free)
Factory
Commercial, 0 to 70°C
CY25200KFZXC
16-Pin TSSOP (Pb-free)
Field
Commercial, 0 to 70°C
CY25200KFZXCT
16-Pin TSSOP – Tape and Reel (Pb-free)
Field
Commercial, 0 to 70°C
CY3672-USB
Programmer for Field Programmable Devices
N/A
N/A
CY3695
CY22050/CY22150/CY25200 Socket Adapter for
CY3672-USB
N/A
N/A
Table 5. 16-Pin TSSOP Package Characteristics
Parameter
Name
Value
Unit
θJA
theta JA
115
°C/W
Package Drawing and Dimensions
Figure 8. 16-Pin TSSOP 4.40 mm Body ZZ16
PIN 1 ID
DIMENSIONS IN MM[INCHES] MIN.
1
MAX.
REFERENCE JEDEC MO-153
6.25[0.246]
6.50[0.256]
PACKAGE WEIGHT 0.05gms
4.30[0.169]
4.50[0.177]
16
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
4.90[0.193]
5.10[0.200]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85091-*A
Notes
5. “xxx” denotes a specific device configuration, and is referred to as the “dash number”. “w” denotes the configuration revision.
6. Not recommended for new designs. Part numbers without a “K” are being replaced by part numbers with a “K”. There are no changes to device specifications as a
result of the part number change.
Document #: 38-07633 Rev. *F
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CY25200
Document History Page
Document Title: CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction
Document Number: 38-07633
REV.
ECN NO.
Orig. of
Change
Submission
Date
**
204243
RGL
See ECN
New data sheet
*A
220043
RGL
See ECN
Minor Change: Corrected letter assignment in the ordering info for Pb free.
Description of Change
*B
267832
RGL
See ECN
Added Field Programmable Devices and Functionality
*C
291094
RGL
See ECN
Added tSKEW spec. and footnote
*D
1821908
DPF/AESA
See ECN
Corrected FSSCLK-Low Voltage specification on page 7 for SSCLK5/6 to
SSCLK1/2/3/4, as SSCLK5/6 output does not operate at low voltage.
Deleted Tccj4 on page 8 for the same reason as above
*E
2442066
KVM/AESA
See ECN
Updated template. Added Note “Not recommended for new designs.”
Added part number CY25200KZXC_XXXW, CY25200KZXC_XXXWT,
CY25200KFZXC in ordering information table. Changed package name to
ZZ16.
*F
2758387
KVM/AESA
09/01/2009
Document #: 38-07633 Rev. *F
Extensive text edits
Replaced Benefits column on page 1 with Description
Revised Table 2 and Table 3 for clarity
Revised the Modulation Frequency paragraph to align with actual software
options and to delete mention of custom frequencies
Corrected 3.3V IOL and IOH values,
Filled in missing units in AC Electrical table
Revised TSKEW footnote for clarity
Removed specific PD# and OE pin nos. from parameters TSTP, TOE1 and TOE2
Standardized timing parameter names to upper case
Corrected part numbers in Ordering Information Table
Removed part number CY25200FZXCT
Added part number CY25200KFZXCT
Replaced CY3672 and CY3672-PRG with CY3672-USB
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CY25200
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at www.cypress.com/sales.
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© Cypress Semiconductor Corporation, 2004-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07633 Rev. *F
Revised September 01, 2009
Page 12 of 12
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