CY25402SXI-XXX

CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum Features ■ ■ ■ ■ ■ ■ Three clock outputs with Programmable drive strength Glitch-free outputs while frequency switching 8-pin SOIC package Commercial and Industrial temperature ranges Two fully integrated phase locked loops (PLLs) Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock Reference Clock input voltage range ❐ 2.5V, 3.0V, and 3.3V for CY25482 ❐ 1.8V for CY25402 and CY25422 Wide operating output frequency range ❐ 3 to 166 MHz Programmable Spread Spectrum with Center and Down Spread option and Lexmark and Linear modulation profiles VDD supply voltage options: ❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482 ❐ 1.8V for CY25422 Selectable output clock voltages independent of VDD: ❐ 2.5V, 3.0V, and 3.3V for CY25402 and CY25482 ❐ 1.8V for CY25422 Frequency Select feature with option to select four different frequencies Power Down, Output Enable, and SS ON/OFF controls Low jitter, high accuracy outputs Ability to synthesize nonstandard frequencies with Fractional-N capability ■ Benefits ■ ■ Multiple high performance PLLs allow synthesis of unrelated frequencies Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies Application specific Programmable EMI reduction using Spread Spectrum for clocks Programmable PLLs for system frequency margin tests Meets critical timing requirements in complex system designs Suitability for PC, consumer, portable, and networking applications Capable of Zero PPM frequency synthesis error Uninterrupted system operation during clock frequency switch Application compatibility in standard and low power systems ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Block Diagram XIN/ EXCLKIN XOUT OSC MUX and FS0 FS1 Control Logic PLL 2 (SS) PLL 1 (SS) Crossbar Switch Output Dividers and Drive Strength Control CLK1 REFOUT CLK2 SSON PD#/OE Cypress Semiconductor Corporation Document #: 001-12565 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 13, 2007 [+] Feedback CY25402/CY25422/CY25482 Table 1. Device Selector Guide Device CY25402 CY25482 CY25422 Crystal Input Yes No Yes EXCKLKIN Input 1.8V LVCMOS 2.5V, 3.0V, 3.3V LVCMOS 1.8V LVCMOS VDD 2.5V, 3.0V, 3.3V 2.5V, 3.0V, 3.3V 1.8V Figure 1. Pin Diagram - CY25402 8-LD SOIC XIN/ EXCLKIN VDD CLK1 REFOUT/ FS0 1 2 3 4 CY25402 8 7 6 5 XOUT GND CLK2/SSON PD#/OE/FS1 Table 1. Pin Definition - CY25402 (2.5V, 3.0V or 3.3V Supply) Pin Number 1 2 3 4 5 6 7 8 Name XIN/EXCLKIN Input VDD CLK1 PD#/OE/FS1 CLK2/SSON GND XOUT Power Output Input Output/Input Power Output IO Power Supply: 2.5V, 3.0V or 3.3V Programmable Clock Output with Spread Spectrum Multifunction Programmable pin: Reference Clock Output or Frequency Select pin Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin Power Supply Ground Crystal Output Description Crystal Input or 1.8V External Clock Input REFOUT/FS0 Output/Input Document #: 001-12565 Rev. *B Page 2 of 10 [+] Feedback CY25402/CY25422/CY25482 Figure 2. Pin Diagram - CY25482 8-LD SOIC EXCLKIN VDD CLK1 REFOUT/ FS0 1 2 3 4 CY25482 8 7 6 5 DNU GND CLK2/SSON PD#/OE/FS1 Table 2. Pin Definition - CY25482 (2.5V, 3.0V or 3.3V Supply) Pin Number 1 2 3 4 5 6 7 8 Name EXCLKIN VDD CLK1 PD#/OE/FS1 CLK2/SSON GND DNU Input Power Output Input Output/Input Power Output IO Power Supply: 2.5V, 3.0V or 3.3V Programmable Clock Output with Spread Spectrum Multifunction Programmable pin: Reference Clock Output or Frequency Select pin Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin Power Supply Ground Do not use this pin Figure 3. Pin Diagram - CY25422 8-LD SOIC XIN/ EXCLKIN VDD CLK1 REFOUT/ FS0 Description 2.5V, 3.0V or 3.3V External Clock Input REFOUT/FS0 Output/Input 1 2 3 4 CY25422 8 7 6 5 XOUT GND CLK2/SSON PD#/OE/FS1 Table 3. Pin Definition - CY25422 (1.8V Supply) Pin Number 1 2 3 4 5 6 7 8 VDD CLK1 REFOUT/FS0 PD#/OE/FS1 CLK2/SSON GND XOUT Name XIN/EXCLKIN Input Power Output Output/Input Input Output/Input Power Output IO Power Supply: 1.8V Programmable Clock Output with Spread Spectrum Multifunction Programmable pin: Reference Clock Output or Frequency Select pin Multifunction Programmable pin: Power Down, Output Enable or Frequency Select pin Multifunction Programmable pin: Programmable Clock Output with Spread Spectrum or Spread Spectrum ON/OFF control pin Power Supply Ground Crystal Output Page 3 of 10 Description Crystal Input or 1.8V External Clock Input Document #: 001-12565 Rev. *B [+] Feedback CY25402/CY25422/CY25482 General Description 2 Configurable PLLs The CY25402, CY25482 and CY25422 have two programmable PLLs that can be used to generate output frequencies ranging from 3 to 166 MHz. The advantage of having two PLLs is that a single device generates two independent frequencies from a single crystal. frequency select inputs, can be used to select among these arbitrarily programmed frequency settings. Each output has programmable output divider options. Glitch-Free Frequency Switch When the frequency select pin, FS(1:0) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is being switched. Input Reference Clocks The input reference clock can be either a crystal or a clock signal, for CY25402 and CY25422 while just a clock signal for CY25482. The input frequency range for crystal (XIN) is 8 MHz to 48 MHz and that for external reference clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the reference clock input for CY25482 is 2.5V/3.0V/3.3V while that for CY25402 and CY25422 is 1.8V. This gives user an option for this device to be compatible for different input clock voltage levels in the system. PD#/OE Mode Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to operate as either frequency select (FS1), power down (PD#) or output enable (OE) mode. PD# is a low-true input. If activated it shuts off the entire chip, resulting in minimum power consumption for the device. Setting this signal high brings the device in the operational mode with default register settings. When this pin is programmed as Output Enable (OE), clock outputs can be enabled or disabled using OE (pin 5). Individual clock outputs can be programmed to be sensitive to this OE pin. VDD Power Supply Options These devices have programmable power supply options. The CY25402/CY25482 is a high voltage part that can be programmed to operate at any voltage 2.5V, 3.0V, or 3.3V while CY25422 is a low voltage part that can operate at 1.8V. Output Drive Strength The DC drive strength of the individual clock output can be programmed for different values. Table 4 shows the typical rise and fall times for different drive strength settings. Table 4. Output Drive Strength Output Drive Strength Low Mid Low Mid High High Rise/Fall Time (ns) (Typical Value) 6.8 3.4 2.0 1.0 Output Source Selection These devices have programmable input sources for each of its clock outputs. There are three available clock sources and these clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock source selection is done by using three out of three crossbar switch. Thus, any one of these three available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have two independent clock outputs. Spread Spectrum Control Both PLLs (PLL1 and PLL2) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK2/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with Lexmark or Linear profile. Generic Configuration and Custom Frequency There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The devices, CY25402, CY25482 and CY25422 can be custom programmed to any desired frequencies and listed features. For customer specific programming, please contact local Cypress Field Application Engineer (FAE) or sales representative. Frequency Select Each PLL can be programmed for up to four different frequencies. There are two multifunction programmable pins, REFOUT/FS0 and PD#/OE/FS1 which if programmed as Document #: 001-12565 Rev. *B Page 4 of 10 [+] Feedback CY25402/CY25422/CY25482 Absolute Maximum Conditions Parameter VDD VDD VIN VIN TS ESDHBM UL-94 MSL Description Supply Voltage for CY25402/CY25482 Supply Voltage for CY25422 Input Voltage for CY25402/CY25482 Input Voltage for CY25422 Temperature, Storage ESD Protection (Human Body Model) Flammability Rating Moisture Sensitivity Level Relative to VSS Relative to VSS Non Functional JEDEC EIA/JESD22-A114-E V-0 @1/8 in. SOIC package Condition Min –0.5 –0.5 –0.5 –0.5 –65 2000 Max 4.5 2.6 VDD+0.5 2.2 +150 10 3 Unit V V V V °C Volts ppm Recommended Operating Conditions Parameter VDD Description VDD Operating Voltage for CY25402/CY25482 Min 2.25 Typ – Max 3.60 Unit V VDD TAC TAI CLOAD tPU VDD Operating Voltage for CY25422 Commercial Ambient Temperature Industrial Ambient Temperature Maximum Load Capacitance Power up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) 1.65 0 –40 – 0.05 1.8 – -– – 1.95 +70 +85 15 500 V °C °C pF ms Document #: 001-12565 Rev. *B Page 5 of 10 [+] Feedback CY25402/CY25422/CY25482 DC Electrical Specifications Parameter VOL Description Output Low Voltage Conditions IOL = 2 mA, drive strength = [00] IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] Min – Typ – Max 0.4 Unit V VOH Output High Voltage IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VDD – 0.4 – – V VIL1 VIL2 VIH1 VIH2 VIH3 Input Low Voltage of PD#/OE, FS0, FS1 and SSON Input Low Voltage of EXCLKIN Input High Voltage of PD#/OE, FS0, FS1 and SSON Input High Voltage of EXCLKIN for CY25402/CY25422 Input High Voltage of EXCLKIN for CY25482 Input Low Current, PD#/OE/FS1 Input High Current, PD#/OE/FS1 VIN = 0V VIN = VDD – – 0.8*VDD 1.62 0.8*VDD – – – 14 100 – – – – – – – – – – – – – 160 12 14 3 – 0.2*VDD 0.18 – 2.2 – 10 10 10 36 250 – – – 7 V V V V V µA µA µA µA kΩ mA mA µA pF IIL IIH IILDN IIHDN RDN IDD[1,2] IDDS [1] Input Low Current, SSON and FS0 pins VIN = 0V (Internal pull down resistor = 160k typ.) Input High Current, SSON and FS0 pins Pull Down Resistor of CLK1, REFOUT/FS0 and CLK2/SSON pins Supply Current for CY25422 Standby Current Input Capacitance VIN = VDD (Internal pull down resistor = 160k typ.) Output clocks in off state by setting PD# = Low PD# = High, No load PD# = Low SSON, PD#/OE/FS1 and FS0 pins Supply Current for CY25402/CY25482 PD# = High, No load CIN[1] Notes 1. Guaranteed by design but not 100% tested 2. Configuration dependent Document #: 001-12565 Rev. *B Page 6 of 10 [+] Feedback CY25402/CY25422/CY25482 AC Electrical Specifications Parameter FIN (crystal) FIN (clock) FCLK DC DC Description Crystal Frequency, XIN Input Clock Frequency (EXCLKIN) Output Clock Frequency Output Duty Cycle, All Clocks except Ref Out Ref Out Duty Cycle Conditions Min 8 8 3 Typ – – – 50 Max 48 166 166 55 Unit MHz MHz MHz % Duty Cycle is defined in Figure 5 on page 8; t1/t2, measured at 50% of VDD Ref In Min 45%, Max 55% 45 40 – – – – – – – 6.8 3.4 2.0 1.0 100 1 60 – – – – – 3 % ns ns ns ns ps ms TRF1 [1] Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Output Rise/Fall Time Cycle-to-cycle Jitter (peak) PLL Lock Time Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [00] Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [01] Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [10] Measured from 20% to 80% of VDD, as shown in Figure 6 on page 8, CLOAD = 15 pF, drive strength [11] Configuration dependent. See Table 5 Measured from 90% of the applied power supply level TRF2[1] TRF3[1] TRF4[1] TCCJ[1,2] TLOCK[1] Table 5. Configuration Example for C-C Jitter Ref. Frequency (MHz) 14.3181 19.2 27 48 CLK1 Output Freq. (MHz) 8.0 74.25 48 48 C-C Jitter Typ (ps) 134 99 67 93 CLK2 Output Freq. (MHz) 48 8 166 166 C-C Jitter Typ (ps) 92 91 103 137 Recommended Crystal Specification for SMD Package Parameter Fmin Fmax R1 C0 CL DL(max) Minimum Frequency Maximum Frequency Motional Resistance (ESR) Shunt Capacitance Parallel Load Capacitance Maximum Crystal Drive Level Description Range 1 Range 2 Range 3 8 14 135 4 18 300 14 28 50 4 14 300 28 48 30 2 12 300 Unit MHz MHz Ω pF pF µW Recommended Crystal Specification for Thru-Hole Package Parameter Fmin Fmax R1 C0 CL DL(max) Minimum Frequency Maximum Frequency Motional Resistance (ESR) Shunt Capacitance Parallel Load Capacitance Maximum Crystal Drive Level Description Range 1 Range 2 Range 3 8 14 90 7 18 1000 14 24 50 7 12 1000 24 32 30 7 12 1000 Unit MHz MHz Ω pF pF µW Document #: 001-12565 Rev. *B Page 7 of 10 [+] Feedback CY25402/CY25422/CY25482 Test and Measurement Setup Figure 4. Test and Measurement Setup V DD 0.1 μ F DUT Outputs C LOAD GND Voltage and Timing Definitions Figure 5. Duty Cycle Definition t1 t2 VDD 50% of VD D C lock O utput 0V Figure 6. Rise Time = TRF, Fall Time = TRF T T RF RF V DD 80% of V DD 20% of VDD 0V Clock Output Document #: 001-12565 Rev. *B Page 8 of 10 [+] Feedback CY25402/CY25422/CY25482 Ordering Information Part Number[3] Pb-free CY25402SXC-xxx CY25402SXC-xxxT CY25482SXC-xxx CY25482SXC-xxxT CY25422SXC-xxx CY25422SXC-xxxT CY25402SXI-xxx CY25402SXI-xxxT CY25482SXI-xxx CY25482SXI-xxxT CY25422SXI-xxx CY25422SXI-xxxT 8-pin SOIC 8-pin SOIC -Tape & Reel 8-pin SOIC 8-pin SOIC -Tape & Reel 8-pin SOIC 8-pin SOIC -Tape & Reel 8-pin SOIC 8-pin SOIC -Tape & Reel 8-pin SOIC 8-pin SOIC -Tape & Reel 8-pin SOIC 8-pin SOIC -Tape & Reel Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 1.8V Supply Voltage: 1.8V Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 2.5V, 3.0V or 3.3V Supply Voltage: 1.8V Supply Voltage: 1.8V Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, -40°C to +85°C Industrial, -40°C to +85°C Industrial, -40°C to +85°C Industrial, -40°C to +85°C Industrial, -40°C to +85°C Industrial, -40°C to +85°C Type VDD(V) Production Flow Package Drawing and Dimensions Figure 7. 8-lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG. 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C 0.0138[0.350] 0.0192[0.487] Note 3. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative. Document #: 001-12565 Rev. *B Page 9 of 10 [+] Feedback CY25402/CY25422/CY25482 Document History Page Document Title: CY25402/CY25422/CY25482 Two PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12565 REV. ** *A *B ECN NO. 690296 815788 1428744 Issue Date See ECN See ECN See ECN Orig. of Change RGL RGL New Data Sheet Minor Change: To post on web Description of Change RGL/AESA Changed data sheet format to match generic part, CY2544/46 Added new device and specification for high ref. input voltage part, CY25482 Removed Preliminary from Title page Replaced CLK2 with REFOUT © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-12565 Rev. *B Revised November 13, 2007 Page 10 of 10 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback