CY25403SXC-008

CY25403/CY25423/CY25483 Three-PLL Programmable Clock Generator with Spread Spectrum Three-PLL Programmable Clock Generator with Spread Spectrum Features ■ Three fully integrated phase-locked loops (PLLs) ■ Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock ■ Reference clock input voltage range ❐ 2.5 V, 3.0 V, and 3.3 V for CY25483 ❐ 1.8 V for CY25403 and CY25423 ■ 8-pin SOIC package ■ Commercial and Industrial temperature ranges ■ One-time programmability For programming support, contact Cypress technical support or send an e-mail to clocks@cypress.com Benefits ■ Multiple high-performance PLLs allow synthesis of unrelated frequencies ■ Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ■ Wide operating output frequency range ❐ 3 to 166 MHz ■ Programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles ■ ■ VDD supply voltage options ❐ 2.5 V, 3.0 V, and 3.3 V for CY25403 and CY25483 ❐ 1.8 V for CY25423 Application specific programmable EMI reduction using Spread Spectrum for clocks ■ Programmable PLLs for system frequency margin tests Frequency select feature with option to select four different frequencies ■ Meets critical timing requirements in complex system designs ■ ■ ■ Power-down, output enable, and SS ON/OFF controls Suitability for PC, consumer, portable, and networking applications Low jitter, high accuracy outputs ■ Capable of Zero PPM frequency synthesis error ■ Ability to synthesize nonstandard frequencies with Fractional-N capability ■ Uninterrupted system operation during clock frequency switch ■ ■ Application compatibility in standard and low-power systems ■ Three clock outputs with programmable drive strength Functional Description ■ Glitch-free outputs while frequency switching For a complete list of related documentation, click here. Block Diagram Crossbar Switch XIN/ EXCLKIN XOUT OSC PLL1 and and FS1 Control CLK1 (SS) Dividers MUX FS0 Output Drive PLL 2 (SS) CLK2 (No SS) Strength Logic Control PLL3 (SS) CLK3 (SS) SSON PD#/OE Cypress Semiconductor Corporation Document Number: 001-12564 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 31, 2017 CY25403/CY25423/CY25483 Contents Device Selector Guide ...................................................... 3 Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 3 Functional Overview ........................................................ 4 Configurable PLLs ....................................................... 4 Input Reference Clocks ............................................... 4 VDD Power Supply Options ........................................ 4 Spread Spectrum Control ............................................ 4 Frequency Select ........................................................ 4 Glitch-Free Frequency Switch ..................................... 4 PD#/OE Mode ............................................................. 4 Output Drive Strength .................................................. 4 Generic Configuration and Custom Frequency ........... 4 Absolute Maximum Conditions ....................................... 5 Recommended Operating Conditions ............................ 5 DC Electrical Specifications ............................................ 6 Thermal Resistance .......................................................... 6 AC Electrical Specifications ............................................ 7 Configuration Example .................................................... 8 Document Number: 001-12564 Rev. *K Recommended Crystal Specification ............................. 8 Recommended Crystal Specification ............................. 8 Test and Measurement Setup .......................................... 9 Voltage and Timing Definitions ....................................... 9 Ordering Information ...................................................... 10 Possible Configurations ............................................. 10 Ordering Code Definitions ......................................... 11 Package Drawing and Dimensions ............................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 16 Worldwide Sales and Design Support ....................... 16 Products .................................................................... 16 PSoC® Solutions ...................................................... 16 Cypress Developer Community ................................. 16 Technical Support ..................................................... 16 Page 2 of 16 CY25403/CY25423/CY25483 Device Selector Guide Device Crystal Input EXCLKIN Input VDD CY25403 Yes 1.8 V LVCMOS 2.5 V, 3.0 V, 3.3 V CY25483 No 2.5 V, 3.0 V, 3.3 V LVCMOS 2.5 V, 3.0 V, 3.3 V CY25423 Yes 1.8 V LVCMOS 1.8 V Pin Configuration Figure 1. 8-pin SOIC pinout CY25403/CY25423/CY25483 XIN/ EXCLKIN 1 VDD 2 CLK1 3 CLK2/FS0 4 CY25403/ CY25423/ CY25483 8 XOUT 7 GND 6 CLK3/SSON 5 PD#/OE/FS1 Pin Definitions CY25403/CY25423/CY25483 Pin Number Name 1 XIN/EXCLKIN Input 2 VDD Power Power supply (Refer Device Selector Guide on page 3) Output Programmable clock output with spread spectrum 3 CLK1 4 CLK2/FS0 5 PD#/OE/FS1 6 CLK3/SSON IO Description Crystal input or external clock input (Refer Device Selector Guide on page 3) Output/Input Multifunction programmable pin: programmable clock output with no spread spectrum or frequency select pin Input Multifunction programmable pin: power-down, output enable, or frequency select pin Output/Input Multifunction programmable pin: programmable clock output with spread spectrum or spread spectrum ON/OFF control pin 7 GND Power Power supply ground 8 XOUT Output Crystal output Document Number: 001-12564 Rev. *K Page 3 of 16 CY25403/CY25423/CY25483 Functional Overview Configurable PLLs The CY25403/CY25423/CY25483 have three programmable PLLs that can be used to generate output frequencies ranging from 3 to 166 MHz. The advantage of having three PLLs is that a single device generates up to three independent frequencies from a single crystal. Input Reference Clocks The input reference clock can be either a crystal or a clock signal, for CY25403 and CY25423 while just a clock signal for CY25483. The input frequency range for crystal (XIN) is 8 MHz to 48 MHz and that for external reference clock (EXCLKIN) is 8 MHz to 166 MHz. The voltage range of the reference clock input for CY25483 is 2.5 V/3.0 V/3.3 V while that for CY25403 and CY25423 is 1.8 V. This gives user an option for this device to be compatible for different input clock voltage levels in the system. VDD Power Supply Options These devices have programmable power supply options. The CY25403/CY25483 is a high voltage part that can be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while CY25423 is a low voltage part that can operate at 1.8 V. These devices have programmable input sources for each of its clock outputs. There are four available clock sources and these clock sources are: XIN/EXCLKIN, PLL1, PLL2, and PLL3. Output clock source selection is done by using four out of four crossbar switch. Thus, any one of these four available clock sources can be arbitrarily selected for the clock outputs. This gives user a flexibility to have up to three independent clock outputs. Glitch-Free Frequency Switch When the frequency select pin, FS(1:0) is used to switch frequency, the outputs are glitch-free provided frequency is switched using output dividers. This feature enables uninterrupted system operation while clock frequency is being switched. PD#/OE Mode Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to operate as either frequency select (FS1), power-down (PD#) or output enable (OE) mode. PD# is a low-true input. If activated it shuts off the entire chip, resulting in minimum power consumption for the device. Setting this signal high brings the device in the operational mode with default register settings. When this pin is programmed as output enable (OE), clock outputs can be enabled or disabled using OE (pin 5). Individual clock outputs can be programmed to be sensitive to this OE pin. Output Drive Strength The DC drive strength of the individual clock output can be programmed for different values. Table 1 shows the typical rise and fall times for different drive strength settings. Table 1. Output Drive Strength Output Drive Strength Rise/Fall Time (ns) (Typical Value) Low 6.8 Mid Low 3.4 Mid High 2.0 High 1.0 Spread Spectrum Control Generic Configuration and Custom Frequency Two of the three PLLs (PLL2 and PLL3) have spread spectrum capability for EMI reduction in the system. The device uses a Cypress proprietary PLL and spread spectrum clock (SSC) technology to synthesize and modulate the frequency of the PLL. The spread spectrum feature can be turned on or off using a multifunction control pin (CLK3/SSON). It can be programmed to either center spread range from ±0.125% to ±2.50% or down spread range from –0.25% to –5.0% with Lexmark or Linear profile. There is a generic set of output frequencies available from the factory that can be used for the device evaluation purposes. The device, CY25403/CY25423/CY25483 can be custom programmed to any desired frequencies and listed features. For customer specific programming, contact your local Cypress Field Application Engineer (FAE) or sales representative. Frequency Select Each PLL can be programmed for up to four different frequencies. There are two multifunction programmable pins, CLK2/FS0 and PD#/OE/FS1 which if programmed as frequency select inputs, can be used to select among these arbitrarily programmed frequency settings. Each output has programmable output divider options. Document Number: 001-12564 Rev. *K Page 4 of 16 CY25403/CY25423/CY25483 Absolute Maximum Conditions Parameter Min Max Unit Supply voltage for CY25403/CY25483 – –0.5 4.5 V Supply voltage for CY25423 – –0.5 2.6 VIN Input voltage for CY25403/CY25423/CY25483 Relative to VSS –0.5 VDD + 0.5 TS Temperature, Storage Non Functional –65 +150 ESDHBM ESD protection (human body model) JEDEC EIA/JESD22-A114-E 2000 UL-94 Flammability rating V-0 at 1/8 in. MSL Moisture sensitivity level SOIC package VDD Description Condition V °C Volts – 10 –3 ppm – Recommended Operating Conditions Parameter VDD Description Min Typ Max Unit V VDD operating voltage for CY25403/CY25483 2.25 – 3.60 VDD operating voltage for CY25423 1.65 1.8 1.95 TAC Commercial ambient temperature TAI Industrial ambient temperature CLOAD Maximum load capacitance tPU Power-up time for all VDD to reach minimum specified voltage (power ramps must be monotonic) Document Number: 001-12564 Rev. *K 0 – +70 °C –40 -- +85 °C – – 15 pF 0.05 – 500 ms Page 5 of 16 CY25403/CY25423/CY25483 DC Electrical Specifications Parameter VOL Description Output low voltage Conditions IOL = 2 mA, drive strength = [00] Min Typ Max Unit – – 0.4 V VDD – 0.4 – – V IOL = 3 mA, drive strength = [01] IOL = 7 mA, drive strength = [10] IOL = 12 mA, drive strength = [11] VOH Output high voltage IOH = –2 mA, drive strength = [00] IOH = –3 mA, drive strength = [01] IOH = –7 mA, drive strength = [10] IOH = –12 mA, drive strength = [11] VIL1 Input low voltage of PD#/OE, FS0, FS1 and SSON – – 0.2 × VDD V VIL2 Input low voltage of EXCLKIN for CY25403/CY25423 – – 0.3 V VIL3 Input low voltage of EXCLKIN for CY25483 – – 0.2 × VDD V VIH1 Input high voltage of PD#/OE, FS0, FS1 and SSON 0.8 × VDD – – V VIH2 Input high voltage of EXCLKIN for CY25403/CY25483 1.62 – 2.2 V VIH3 Input high voltage of EXCLKIN for CY25423 0.8 × VDD – – V IIL Input low current, PD#/OE/FS1 – – 10 µA IIH – – 10 µA IILDN Input high current, PD#/OE/FS1 VIN = VDD Input low current, SSON and FS0 VIN = 0 V pins (Internal pull-down resistor = 160k typ.) – – 10 µA IIHDN Input high current, SSON and FS0 pins 14 – 36 µA RDN Pull-down resistor of CLK1, Output clocks in off state by setting CLK2/FS0 and CLK3/SSON pins PD# = Low 100 160 250 k IDD[1, 2] Supply current for CY25403/CY25423/CY25483 PD# = High, No load – 22 – mA IDDS[1] Standby current PD# = Low – 3 – µA CIN[1] Input capacitance SSON, PD#/OE/FS1 and FS0 pins – – 7 pF VIN = 0 V VIN = VDD (Internal pull-down resistor = 160k typ.) Thermal Resistance Parameter [3] Description θJA Thermal resistance (junction to ambient) θJC Thermal resistance (junction to case) Test Conditions 8-pin SOIC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 131 °C/W 40 °C/W Notes 1. Guaranteed by design but not 100% tested. 2. Configuration dependent. 3. These parameters are guaranteed by design and are not tested. Document Number: 001-12564 Rev. *K Page 6 of 16 CY25403/CY25423/CY25483 AC Electrical Specifications Min Typ Max Unit FIN (crystal) Parameter Crystal frequency, XIN Description – Conditions 8 – 48 MHz FIN (clock) Input clock frequency (EXCLKIN) – 8 – 166 MHz FCLK Output clock frequency – 3 – 166 MHz DC Output duty cycle, all clocks except ref out Duty Cycle is defined in Figure 3 on page 9; t1/t2, measured at 50% of VDD 45 50 55 % DC Ref out duty cycle Ref In Min 45%, Max 55% 40 – 60 % TRF1[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 9, CL = 15 pF, drive strength [00] – 6.8 – ns TRF2[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 9, CL = 15 pF, drive strength [01] – 3.4 – ns TRF3[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 9, CL = 15 pF, drive strength [10] – 2.0 – ns TRF4[4] Output rise/fall time Measured from 20% to 80% of VDD, as shown in Figure 4 on page 9, CL = 15 pF, drive strength [11] – 1.0 – ns TCCJ[4, 5] Cycle-to-cycle jitter (peak) Configuration dependent. See Configuration Example on page 8 – 100 – ps TLOCK[4] PLL lock time Measured from 90% of the applied power supply level – 1 3 ms Notes 4. Guaranteed by design but not 100% tested. 5. Configuration dependent. Document Number: 001-12564 Rev. *K Page 7 of 16 CY25403/CY25423/CY25483 Configuration Example For C-C Jitter Ref. Frequency (MHz) CLK1 Output CLK2 Output Freq. (MHz) C-C Jitter Typ (ps) 14.3181 8.0 19.2 74.25 27 48 CLK3 Output Freq. (MHz) C-C Jitter Typ (ps) Freq. (MHz) C-C Jitter Typ (ps) 134 166 103 48 92 99 166 94 8 91 48 67 27 109 166 103 48 93 27 123 166 137 Recommended Crystal Specification For SMD Package Parameter Fmin Description Minimum frequency Range 1 Range 2 Range 3 Unit 8 14 28 MHz Fmax Maximum frequency 14 28 48 MHz R1 Motional resistance (ESR) 135 50 30  C0 Shunt capacitance 4 4 2 pF CL Parallel load capacitance 18 14 12 pF DL(max) Maximum crystal drive level 300 300 300 µW Range 1 Range 2 Range 3 Unit 8 14 24 MHz Recommended Crystal Specification For Thru-Hole Package Parameter Fmin Description Minimum frequency Fmax Maximum frequency 14 24 32 MHz R1 Motional resistance (ESR) 90 50 30  C0 Shunt capacitance 7 7 7 pF CL Parallel load capacitance 18 12 12 pF DL(max) Maximum crystal drive level 1000 1000 1000 µW Document Number: 001-12564 Rev. *K Page 8 of 16 CY25403/CY25423/CY25483 Test and Measurement Setup Figure 2. Test and Measurement Setup V DD 0.1 F Outputs C LOAD DUT GND Voltage and Timing Definitions Figure 3. Duty Cycle Definition t1 t2 V DD 50% of VDD Clock Output 0V Figure 4. Rise Time = TRF, Fall Time = TRF T RF T RF V DD 80% of V DD Clock Output Document Number: 001-12564 Rev. *K 20% of VDD 0V Page 9 of 16 CY25403/CY25423/CY25483 Ordering Information Part Number Type Package Supply Voltage Production Flow Pb-free CY25403SXC Field Programmable 8-pin SOIC 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25403SXCT Field Programmable 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25423SXC Field Programmable 8-pin SOIC 1.8 V Commercial, 0 °C to 70 °C CY25423SXCT Field Programmable 8-pin SOIC – Tape and Reel 1.8 V Commercial, 0 °C to 70 °C CY25483SXC Field Programmable 8-pin SOIC CY25483SXCT Field Programmable 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25403SXI Field Programmable 8-pin SOIC CY25403SXIT Field Programmable 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25423SXI Field Programmable 8-pin SOIC 1.8 V Industrial, –40 °C to +85 °C CY25423SXIT Field Programmable 8-pin SOIC – Tape and Reel 1.8 V Industrial, –40 °C to +85 °C CY25483SXI Field Programmable 8-pin SOIC CY25483SXIT Field Programmable 8-pin SOIC – Tape and Reel 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C Programmer CY3675-CLKMAKER1 Programming Kit CY3675-SOIC8A Socket Adapter Board, for programming CY25402, CY25403, CY25422, CY25423, CY25482, and CY25483 Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or sales representative for more information. Possible Configurations Part Number[6] Type VDD(V) Production Flow Pb-free CY25403/CY25423/CY25483SXC- 8-pin SOIC xxx Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C CY25403/CY25423/CY25483SXC- 8-pin SOIC – Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Commercial, 0 °C to 70 °C xxxT CY25403/CY25423/CY25483SXI-x 8-pin SOIC xx Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C CY25403/CY25423/CY25483SXI-x 8-pin SOIC – Tape and Reel Supply Voltage: 2.5 V, 3.0 V, or 3.3 V Industrial, –40 °C to +85 °C xxT Note 6. xxx indicates factory programmed parts based on customer specific configuration. For more details, contact your local Cypress FAE or sales representative. Document Number: 001-12564 Rev. *K Page 10 of 16 CY25403/CY25423/CY25483 Ordering Code Definitions CY254x3 SX C/I - xxx T Package Type: (T = Tape and Reel) Customer Specific Identification Code Temperature Code (C = Commercial or I = Industrial) 8-pin SOIC package (Pb-free) Marketing Code: CY25403/23/83 = Device Number Document Number: 001-12564 Rev. *K Page 11 of 16 CY25403/CY25423/CY25483 Package Drawing and Dimensions Figure 5. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *I Document Number: 001-12564 Rev. *K Page 12 of 16 CY25403/CY25423/CY25483 Acronyms Acronym Document Conventions Description Units of Measure DL drive level DNU do not use °C degree Celsius DUT device under test MHz megahertz EIA Electronic Industries Alliance µA microampere EMI electromagnetic interference mA milliampere ESD electrostatic discharge ms millisecond FAE field application engineer ns nanosecond FS frequency select JEDEC Joint Electron Devices Engineering Council LVCMOS low voltage complementary metal oxide semiconductor OE output enable OSC oscillator PD power-down PLL phase-locked loop PPM parts per million SS spread spectrum SSC spread spectrum clock SSON spread spectrum on Document Number: 001-12564 Rev. *K Symbol Unit of Measure pF picofarad ps picosecond V volt Page 13 of 16 CY25403/CY25423/CY25483 Document History Page Document Title: CY25403/CY25423/CY25483, Three-PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12564 Rev. ECN No. Orig. of Change Submission Date ** 690296 RGL 01/17/2007 Description of Change New data sheet. *A 815788 RGL 03/02/2007 Minor Change: To post on web. *B 1428744 RGL / AESA 08/30/2007 Updated Document Title to read as “CY25403/CY25423/CY25483 Three PLL Programmable Clock Generator with Spread Spectrum”. Changed status from Preliminary to Final. Added CY25483 part related information in all instances across the document. Updated Block Diagram. Updated Pin Definitions: Updated details in “Description” column. Updated Functional Overview: Updated description and added sub-sections. Updated Absolute Maximum Conditions: Updated details corresponding to VDD and VIN parameters. Updated Recommended Operating Conditions: Updated details corresponding to VDD parameter. Updated DC Electrical Specifications: Updated almost entire table. Updated Ordering Information: Updated part numbers. *C 2748211 TSAI 08/10/2009 Post to external web. *D 2899300 CXQ 03/25/2010 Updated Ordering Information: Added Possible Configurations. Added Note 6 and referred the same note in “Part Number” column. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *C to *D. *E 2898568 CXQ 06/02/2010 Updated Ordering Information: Updated part numbers. Added Ordering Code Definitions. Added Acronyms. Updated to new template. *F 3319132 BASH 07/18/2011 Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *D to *E. Added Units of Measure. Updated to new template. Document Number: 001-12564 Rev. *K Page 14 of 16 CY25403/CY25423/CY25483 Document History Page (continued) Document Title: CY25403/CY25423/CY25483, Three-PLL Programmable Clock Generator with Spread Spectrum Document Number: 001-12564 Rev. ECN No. Orig. of Change Submission Date Description of Change *G 4468493 TAVA 08/12/2014 Updated Features: Updated details under “Reference clock input voltage range”, “VDD supply voltage options:”, and “Selectable output clock voltages independent of VDD supply:”. Updated Device Selector Guide: Updated details in “Crystal Input”, “EXCLKIN Input” and “VDD” columns. Updated Pin Definitions: Updated details in “Description” column corresponding to pin numbers 1 and 2. Updated Functional Overview: Updated Input Reference Clocks: Updated description. Updated VDD Power Supply Options: Updated description. Updated Absolute Maximum Conditions: Updated details corresponding to VDD parameter. Updated Recommended Operating Conditions: Updated details corresponding to VDD parameter. Updated DC Electrical Specifications: Updated details corresponding to VIH2 parameter. Added VIH3 parameter and its details. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *E to *F. Updated to new template. Completing Sunset Review. *H 4586478 TAVA 12/03/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *I 5279365 PSR 05/20/2016 Added Thermal Resistance. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *F to *H. Updated to new template. Completing Sunset Review. *J 5778174 PSR 06/19/2017 Updated Features: Added one-time programmability. *K 5952739 XHT 10/31/2017 Updated DC Electrical Specifications: Updated details in “Description” and “Max” columns corresponding to VIL2 parameter. Added VIL3 parameter and its details. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *H to *I. Updated to new template. Document Number: 001-12564 Rev. *K Page 15 of 16 CY25403/CY25423/CY25483 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 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Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 001-12564 Rev. *K Revised October 31, 2017 Page 16 of 16