CY25560SXIT

CY25560 Spread Spectrum Clock Generator Features • 25- to 100-MHz operating frequency range • Wide (9) range of spread selections • Accepts clock and crystal inputs • Low power dissipation: — 56 mW @ Fin = 25 MHz — 89 mW @ Fin = 65 MHz — 139 mW @ Fin = 100 MHz • Frequency spread disable function • Center spread modulation • Low cycle-to cycle jitter • 8-pin SOIC package • Commercial and Industrial temperature ranges Applications • Desktop, notebook, and tablet PCs • VGA controllers • LCD panels and monitors • Printers and multifunction devices (MFP) Benefits • Peak electromagnetic interference (EMI) reduction by 8 to 16 dB • Fast time to market • Cost reduction Block Diagram Pin Configuration 250 K Xin/ CLK 1 REFERENCE DIVIDER PD CP Loop Filter XIN/CLK 1 VDD 2 VSS 3 SSCLK 4 8 XOUT 7 S0 Xout 8 CY25560 6 S1 5 SSCC MODULATION CONTROL FEEDBACK DIVIDER vco VDD 2 3 INPUT DECODER LOGIC VDD 20 K VDD 20 K DIVIDER & MUX 4 SSCLK VSS 20 K 20 K 5 SSCC VSS 6 S1 7 S0 VSS Cypress Semiconductor Corporation Document #: 38-07425 Rev. *D • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 28, 2005 CY25560 Pin Description Pin Number Pin Name 1 2 3 4 5 6 Xin/CLK VDD GND SSCLK SSCC S1 Type I P P O I I Positive power supply. Power supply ground. Modulated clock output which is the same frequency as the input clock or the crystal frequency. Spread Spectrum Clock Control (Enable/Disable) function. SSCG function is enabled when input is HIGH and disabled when input is LOW. This pin is pulled HIGH internally. Tri-level logic input control pin used to select input frequency range and spread percent. Refer to tri-level logic on page 3 for programming details. Pin 6 has internal resistor divider network to VDD and VSS. Refer to Block Diagram on page 1. Tri-level logic input control pin used to select input frequency range and spread percent. Refer to tri-level logic on page 3 for programming details. Pin 7 has internal resistor divider network to VDD and VSS. Refer to Block Diagram on page 1. Oscillator output pin connected to crystal. Leave this pin unconnected if an external clock is used to drive XIN/CLK input (pin-1). one of the nine available Spread% ranges. Refer to Table 1 for programming details. The CY25560 is optimized for SVGA (40-MHz) and XVGA (65-MHz) Controller clocks and also suitable for the applications where the frequency range is 25 to 100 MHz. A wide range of digitally selectable spread percentages is made possible by using three-level (High, Low, and Middle) logic at the S0 and S1 digital control inputs. The output spread (frequency modulation) is symmetrically centered on the input frequency. Spread Spectrum Clock Control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing. The CY25560 is available in an eight-pin SOIC package with 0°C to 70°C commercial and –40°C to 85°C Industrial operating temperature ranges. Pin Description Clock or crystal connection input. Refer to Table 1 for input frequency range selection. 7 S0 I 8 Xout O General Description The Cypress CY25560 is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing EMI found in today’s high-speed digital electronic systems. The CY25560 uses a Cypress proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies of Clock (SSCLK) is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading the system performance. The CY25560 is a very simple and versatile device to use. The frequency and spread% range is selected by programming S0 and S1 digital inputs. These inputs use three (3) logic states including High (H), Low (L) and Middle (M) logic levels to select Table 1. Frequency and Spread% Selection (Center Spread) 25 – 50 MHz (Low Range) Input Frequency (MHz) 25 – 35 35 – 40 40 – 45 45 – 50 S1=M S0=M (%) 4.3 3.9 3.7 3.4 S1=M S0=0 (%) 3.8 3.5 3.3 3.1 S1=1 S0=0 (%) 3.4 3.1 2.8 2.6 S1=0 S0=0 (%) 2.9 2.5 2.4 2.2 S1=0 S0=M (%) 2.8 2.4 2.3 2.1 Select the Frequency and Center Spread % desired and then set S1, S0 as indicated. 50 – 100 MHz (High Range) Input Frequency (MHz) 50 – 60 60 – 70 70 – 80 80 – 100 S1=1 S0=M (%) 2.9 2.8 2.6 2.4 S1=0 S0=1 (%) 2.1 2.0 1.8 1.7 S1=1 S0=1 (%) 1.5 1.4 1.3 1.2 S1=M S0=1 (%) 1.2 1.1 1.1 1.0 Select the Frequency and Center Spread % desired and then set S1, S0 as indicated. Document #: 38-07425 Rev. *D Page 2 of 8 CY25560 CY25560 S0 = "M" (N/C) 7 S0 S0 = "1" S1 S1 = "0" (GND) VDD SSCC = "1" 5 SSCC = "1" 5 6 VDD SSCC = "1" 5 CY25560 7 S0 VDD CY25560 S0 = "1" 7 S0 VDD S1 = "0" (GND) 6 S1 S1 = "1" 6 S1 Figure 1. Three-level Logic Examples Tri-level Logic With binary logic, four states can be programmed with two control lines whereas three-level logic can program nine logic states using two control lines. Three-level logic in the CY25560 is implemented by defining a third logic state in addition to the standard logic “1” and “0.” Pins 6 and 7 of the CY25560 recognize a logic state by the voltage applied to the respective pin. These states are defined as “0” (Low), “M” (Middle), and “1” (One). Each of these states have a defined voltage range that is interpreted by the CY25560 as a “0”, “M” or “1” logic state. Refer to Table 2 for voltage ranges for each logic state. The CY25560 has two equal value resistor dividers connected internally to Pins 6 and 7 that produce the default “M” (Middle) state if these pins are left unconnected (NC). Pins 6 and/or 7 can be tied directly to ground or VDD to program a Logic “0” or “1” state, respectively. SSCG SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both peak and cycle to cycle. The CY25560 takes a narrow band digital reference clock in the range of 25–100 MHz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. To understand what happens to a clock when SSCG is applied, consider a 65-MHz clock with a 50% duty cycle. From a 65-MHz clock we know the following: Clock Frequency = fc = 200 MHz Clock Period = Tc =1/200 MHz = 5.0 ns. 5% 0 5% 0 T =5 n c .0 s SSCG Theory of Operation The CY25560 is a PLL-type clock generator using a proprietary Cypress design. By precisely controlling the bandwidth of the output clock, the CY25560 becomes a Low-EMI clock generator. The theory and detailed operation of the CY25560 will be discussed in the following sections. EMI All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50%. Because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in the odd harmonics, i.e., third, fifth, seventh, etc. It is possible to reduce the amount of energy contained in the fundamental and odd harmonics by increasing the bandwidth of the fundamental clock frequency. Conventional digital clocks have a very high Q factor, which means that all of the energy at that frequency is concentrated in a very narrow bandwidth, consequently, higher energy peaks. Regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for EMI. Conventional methods of reducing EMI have been to use shielding, filtering, multilayer PCBs, etc. The CY25560 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the Q. If this clock is applied to the Xin/CLK pin of CY25560, the output clock at pin 4 (SSCLK) will be sweeping back and forth between two frequencies. These two frequencies, F1 and F2, are used to calculate to total amount of spread or bandwidth applied to the reference clock at pin 1. As the clock is making the transition from F1 to F2, the amount of time and sweep waveform play a very important role in the amount of EMI reduction realized from an SSCG clock. The modulation domain analyzer is used to visualize the sweep waveform and sweep period. Figure 2 shows the modulation profile of a 65 MHz SSCG clock. Notice that the actual sweep waveform is not a simple sine or sawtooth waveform. Figure 2 also shows a scan of the same SSCG clock using a spectrum analyzer. In this scan you can see a 6.48-dB reduction in the peak RF energy when using the SSCG clock. Modulation Rate Spectrum Spread Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the Modulation Rate, Tmod. Modulation Rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the Modulation Rate. In some SSCG clock generators, the selected range determines the internal divider count. In other SSCG clocks, the internal divider count is fixed over the operating range of the part. The CY25560 has a fixed divider count of 1166. Page 3 of 8 Document #: 38-07425 Rev. *D CY25560 Device CY25560 Cdiv 1166 (All Ranges) Example: Device = CY25560 Fin = 65 MHz Range = S1 = 1, S0 = 0 Then; Modulation Rate = Fmod = 65 MHz/1166 = 55.7 kHz. Modulation Profile Spectrum Analyzer Figure 2. SSCG Clock, CY25560, Fin = 65 MHz CY25560 Application Schematic VDD C3 0.1 uF 2 C2 1 Y1 30 M H z 8 X IN /C LK VDD S S C LK 4 27 pF C3 XOUT 27 pF C Y 25560 5 S1 SSCC VSS 3 6 VDD S0 7 Figure 3. Application Schematic The schematic in Figure 3 above demonstrates how the CY25560 is configured in a typical application. This application is shown as using a 30-MHz fundamental crystal. In most applications an external reference clock is used. Apply the external clock signal at Xin (pin 1) and leave Xout (pin 8) unconnected. Contact Cypress if higher-order crystal is to be used. Document #: 38-07425 Rev. *D Page 4 of 8 CY25560 Absolute Maximum Ratings (Commercial Grade)[1, 2] Supply Voltage (VDD): .................................... –0.5V to +6.0V DC Input Voltage:....................................–0.5V to VDD+0.5V Junction Temperature ................................. –40°C to +140°C Operating Temperature: ...................................... 0°C to 70°C DC Electrical Characteristics VDD = 3.3V±10%, T= 0°C to 70°C and CL (Pin 4) = 15 pF, unless otherwise noted Parameter VDD VIH VIM VIL VOH VOL Cin1 Cin2 Cin2 IDD1 IDD2 IDD3 Description Power Supply Range Input High Voltage Input Middle Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Capacitance Input Capacitance Input Capacitance Power Supply Current Power Supply Current Power Supply Current ±10% S0 and S1 only S0 and S1 only S0 and S1 only IOH = 6 ma IOH = 6 ma Xin/CLK (Pin 1) Xout (Pin 8) S0, S1, SSCC (Pins 7, 6, 5) FIN = 25 MHz, CL= 0 FIN = 65 MHz, CL= 0 FIN = 100 MHz, CL= 0 3 6 3 4 8 4 17 27 42 Conditions Min. 2.97 0.85VDD 0.40VDD 0.0 2.4 0.4 5 10 5 23 41 59 Typ. 3.3 VDD 0.50VDD 0.0 Max. 3.63 VDD 0.60VDD 0.15VDD Unit V V V V V V pF pF pF mA mA mA Storage Temperature .................................. –65°C to +150°C Static Discharge Voltage(ESD)............................ 2,000V-Min Table 2. Electrical Timing Characteristics VDD = 3.3V±10%, T= 0°C to 70°C and CL (Pin 4) = 15 pF, unless otherwise noted Parameter ICLKFR tF tR DTYin DTYout JCC1 JCC2 Description Input Clock Frequency Range Clock Rise Time (Pin 4) Clock Fall Time (Pin 4) Input Clock Duty Cycle Output Clock Duty Cycle Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter VDD = 3.30V SSCLK @ 0.4 – 2.4V SSCLK @ 0.4 – 2.4V XIN/CLK (Pin 1) SSCLK (Pin 4) Fin = 25–50 MHz, SSCC = 1 Fin = 50–100 MHz, SSCC = 1 Conditions Min. 25 1.0 1.0 25 45 1.8 1.8 50 50 150 130 Typ. Max. 100 2.8 2.8 75 55 300 200 Unit MHz ns ns % % ps ps Notes: 1. Operation at any Absolute Maximum Rating is not implied. 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power up. Document #: 38-07425 Rev. *D Page 5 of 8 CY25560 Absolute Maximum Conditions (Industrial Grade)[1, 2] Supply Voltage (VDD): .................................... –0.5V to +6.0V DC Input Voltage:....................................–0.5V to VDD+0.5V Junction Temperature ................................. –40°C to +140°C Operating Temperature:.................................. –40°C to 85°C Storage Temperature .................................. –65°C to +150°C Static Discharge Voltage(ESD)............................ 2,000V-Min Table 3. DC Electrical Characteristics (Preliminary) VDD = 3.3V±10%, T= –40°C to 85°C and CL (Pin 4) = 15 pF, unless otherwise noted Parameter VDD VIH VIM VIL VOH VOL Cin1 Cin2 Cin2 IDD1 IDD2 IDD3 Description Power Supply Range Input High Voltage Input Middle Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Capacitance Input Capacitance Input Capacitance Power Supply Current Power Supply Current Power Supply Current ±10% S0 and S1 only S0 and S1 only S0 and S1 only IOH = 6 ma IOH = 6 ma Xin/CLK (Pin 1) Xout (Pin 8) S0, S1, SSCC (Pins 7, 6, 5) FIN = 25 MHz, CL= 0 FIN = 65 MHz, CL= 0 FIN = 100 MHz, CL= 0 3 6 3 4 8 4 17 27 42 Conditions Min. 2.97 0.85VDD 0.40VDD 0.0 2.2 0.4 5 10 5 24 41 61 Typ. 3.3 VDD 0.50VDD 0.0 Max. 3.63 VDD 0.60VDD 0.15VDD Unit V V V V V V pF pF pF mA mA mA Table 4. Electrical Timing Characteristics (Preliminary) VDD = 3.3V±10%, T= –40°C to 85°C and CL (Pin 4) = 15 pF, unless otherwise noted Parameter ICLKFR tF tR DTYin DTYout JCC1 JCC2 Description Input Clock Frequency Range Clock Rise Time (Pin 4) Clock Fall Time (Pin 4) Input Clock Duty Cycle Output Clock Duty Cycle Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter VDD = 3.30V SSCLK @ 0.4 – 2.4V SSCLK @ 0.4 – 2.4V XIN/CLK (Pin 1) SSCLK (Pin 4) Fin = 25–50 MHz, SSCC = 1 Fin = 50–100 MHz, SSCC = 1 Conditions Min. 25 1.0 1.0 25 45 1.8 1.8 50 50 150 130 Typ. Max. 100 3.0 3.0 75 55 300 200 Unit MHz ns ns % % ps ps Ordering Information Part Number CY25560SC CY25560SCT CY25560SI CY25560SIT Lead-free CY25560SXC CY25560SXCT CY25560SXI CY25560SXIT 8-pin SOIC 8-pin SOIC–Tape and Reel 8-pin SOIC 8-pin SOIC–Tape and Reel Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C 8-pin SOIC 8-pin SOIC–Tape and Reel 8-pin SOIC 8-pin SOIC–Tape and Reel Package Type Product Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, –40°C to 85°C Industrial, –40°C to 85°C Document #: 38-07425 Rev. *D Page 6 of 8 CY25560 Package Drawing and Dimensions 8 Lead (150 Mil) SOIC S08 8-lead (150-Mil) SOIC S8 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 5 8 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85066-*C 0.0138[0.350] 0.0192[0.487] All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07425 Rev. *D Page 7 of 8 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY25560 Document History Page Document Title:CY25560 Spread Spectrum Clock Generator Document Number: 38-07245 Rev. ** *A *B *C ECN No. 115261 119441 122704 125549 Issue Date 06/12/02 10/17/02 12/30/02 05/15/03 Orig. of Change OXC RGL RBI RGL New Data Sheet Corrected the values in the Absolute Maximum Ratings to match the device. Added power up requirements to maximum ratings information. Added Industrial Temperature Range to the device. Removed VOL2 and VOH2 spec in the DC specs table Changed IDD Values from 11/17/25 typ and 14/22/34max to 17/27/42 typ and 23/41/59 max Changed TF/TR values from 1.3/1.3 typ and 1.6/1.6 max to 1.8/1.8 typ and 2.8/2.8 max in the Electrical Char. table. Changed JCC1/2 values from 200/250 typ and 250/300 max to 150/130 typ to 300/200 max in the Electrical Char. table. Changed the low power dissipation from 36/56/82mW to 56/89/139mW respectively. Changed the low cycle-to-cycle jitter from 195/175/100ps-typ to 450/225/150 ps-max Added Lead-free devices Description of Change *D 314293 See ECN RGL Document #: 38-07425 Rev. *D Page 8 of 8