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CY25561SXCT

CY25561SXCT

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

    SOICN-8_4.9X3.9MM

  • 描述:

    IC CLOCK GEN 3.3V SS 8-SOIC

  • 数据手册
  • 价格&库存
CY25561SXCT 数据手册
CY25561 Spread Spectrum Clock Generator Spread Spectrum Clock Generator Features ■ 50 to 166 MHz operating frequency range ■ Wide range of spread selections: 9 ■ Accepts clock and crystal inputs ■ Low power dissipation ❐ 70 mW - Typ at 66 MHz ■ Frequency spread disable function ■ Center spread modulation ■ Low cycle-to-cycle jitter ■ 8-pin SOIC Package This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements and time to market without degrading the system performance. CY25561 is a very simple and versatile device to use. The frequency and spread percentage range is selected by programming S0 and S1 digital inputs. These inputs use three logic states including high (H), low (L), and middle (M) logic levels to select one of the nine available spread percentage ranges. Refer to Frequency and Spread Percentage Selection (Center Spread) on page 3 for programming details. CY25561 is intended for use with applications with a reference frequency in the range of 50 to 166 MHz. A wide range of digitally selectable spread percentages is made possible by using tri-level (high, low, and middle) logic at the S0 and S1 digital control inputs. Functional Description CY25561 is a spread spectrum clock generator (SSCG) IC used to reduce electromagnetic Interference (EMI) found in today’s high speed digital electronic systems. CY25561 uses a Cypress proprietary phase-locked loop (PLL) and spread spectrum clock (SSC) technology to synthesize and frequency modulate the input frequency of the reference clock. By doing this, the measured EMI at the fundamental and harmonic frequencies of clock (SSCLK) is reduced. The output spread (frequency modulation) is symmetrically centered on the input frequency. Spread spectrum clock control (SSCC) function enables or disables the frequency spread and is provided for easy comparison of system performance during EMI testing. CY25561 is available in an eight-pin SOIC package with a 0 °C to 70 °C operating temperature range. For a complete list of related documentation, click here. Logic Block Diagram 300 K Xin/ CLK 1 Xout 8 VDD VSS REFERENCE DIVIDER PD MODULATION CONTROL 2 FEEDBACK DIVIDER INPUT DECODER LOGIC 3 vco DIVIDER & MUX VDD VDD 20K 20K 20K Loop Filter CP 4 SSCLK 20K VSS VSS 5 6 7 SSCC S1 S0 Note: Refer to the CY25560 data sheet for operation at frequencies from 25 to100 MHz. Cypress Semiconductor Corporation Document Number: 38-07242 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 8, 2018 CY25561 Contents Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 3 Frequency and Spread Percentage Selection (Center Spread) ................................................................. 3 Tri-level Logic ................................................................... 4 SSCG Theory of Operation .............................................. 4 EMI .............................................................................. 4 SSCG .......................................................................... 4 Modulation Rate .......................................................... 5 CY25561 Application Schematic ..................................... 6 Absolute Maximum Ratings ............................................ 7 DC Electrical Characteristics .......................................... 7 Thermal Resistance .......................................................... 7 XIN/CLK DC Specifications .............................................. 8 Electrical Timing Characteristics .................................... 8 Document Number: 38-07242 Rev. *K Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Drawing and Dimensions ............................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC® Solutions ...................................................... 13 Cypress Developer Community ................................. 13 Technical Support ..................................................... 13 Page 2 of 13 CY25561 Pin Configuration Figure 1. 8-pin SOIC pinout XIN/CLK 1 8 XOUT VDD 2 7 S0 CY25561 VSS 3 6 S1 SSCLK 4 5 SSCC Pin Definitions Pin Name Type Description 1 XIN / CLK I Clock or crystal connection input. Refer to Frequency and Spread Percentage Selection (Center Spread) for input frequency range selection. 2 VDD P Positive power supply 3 VSS P Power supply ground 4 SSCLK O Modulated clock output 5 SSCC I Spread spectrum clock control (enable/disable) function. SSCG function is enabled when input is high and disabled when input is low. This pin is pulled high internally. 6 S1 I Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth selection and tri-level logic programming. See Figure 2. Pin 6 has internal resistor divider network to VDD and VSS. Refer to Logic Block Diagram on page 1. 7 S0 I Tri-level logic input control pin used to select frequency and bandwidth. Frequency/Bandwidth selection and tri-level logic programming. See Figure 2. Pin 7 has internal resistor divider network to VDD and VSS. Refer to Logic Block Diagram on page 1. 8 XOUT O Oscillator output pin connected to crystal. Leave this pin unconnected If an external clock drives XIN / CLK. Frequency and Spread Percentage Selection (Center Spread) 50–100 MHz (Low Range) Input Frequency (MHz) 50–60 60–70 70–80 80–100 S1=M S0=M (%) 4.3 4.0 3.8 3.5 S1=M S0=0 (%) 3.9 3.6 3.4 3.1 S1=1 S0=0 (%) 3.3 3.1 2.9 2.7 S1=0 S0=0 (%) 2.9 2.6 2.5 2.2 S1=0 S0=1 (%) 2.4 2.1 2.0 2.0 1.8 S1=1 S0=1 (%) 1.5 1.4 1.3 1.3 1.2 S1=M S0=1 (%) 1.3 1.1 1.1 1.1 1.0 S1=0 S0=M (%) 2.7 2.5 2.4 2.1 Select the Frequency and Center Spread % desired and then set S1, S0 as indicated. 100–166 MHz (High Range) Input Frequency (MHz) 100–120 120–130 130–140 140–150 150–166 S1=1 S0=M (%) 3.0 2.7 2.6 2.6 2.5 Document Number: 38-07242 Rev. *K Select the Frequency and Center Spread % desired and then set S1, S0 as indicated. Page 3 of 13 CY25561 Tri-level Logic With binary logic, four states can be programmed with two control lines, whereas tri-level logic can program nine logic states using two control lines. Tri-level logic in CY25561 is implemented by defining a third logic state in addition to the standard logic “1” and “0”. Pins 6 and 7 of CY25561 recognize a logic state by the voltage applied to the respective pin. These states are defined as “0” (low), “M” (middle), and “1” (one). Each of these states has a defined voltage range that is interpreted by CY25561 as a “0,” “M,” or “1” logic state. Refer to DC Electrical Characteristics on page 7 for voltage ranges for each logic state. CY25561 has two equal value resistors connected internally to pin 6 and pin 7 that produce the default “M” state. Pins 6 and/or 7 can be tied directly to ground or VDD to program a logic “0” or “1” state, respectively. Refer to Figure 2 for examples. Figure 2. Tri-level Logic Examples VDD CY25561 CY25561 S0 = "M" (N/C) 7 S1 = "0" (GND) 6 SSCC = "1" 5 S0 S0 = "1" 7 S1 S0 S0 = "1" 7 S1 = "1" 6 SSCC = "1" 5 S0 S1 S1 = "0" (GND) 6 VDD S1 VDD SSCC = "1" 5 SSCG Theory of Operation CY25561 is a PLL-type clock generator using a proprietary Cypress design. By precisely controlling the bandwidth of the output clock, CY25561 becomes a low-EMI clock generator. The theory and detailed operation of CY25561 is discussed in the following sections. peak and cycle-to-cycle. CY25561 takes a narrow band digital reference clock in the range of 50 to166 MHz and produces a clock that sweeps between a controlled start and stop frequency and precise rate of change. To understand what happens to a clock when SSCG is applied, consider a 65 MHz clock with a 50 percent duty cycle, as shown in the following figure: EMI All digital clocks generate unwanted energy in their harmonics. Conventional digital clocks are square waves with a duty cycle that is very close to 50 percent. Because of this 50/50 duty cycle, digital clocks generate most of their harmonic energy in odd harmonics, that is; third, fifth, seventh, etc. The amount of energy contained in the fundamental and odd harmonics can be reduced by increasing the bandwidth of the fundamental clock frequency. Conventional digital clocks have a very high Q factor; all the energy at that frequency is concentrated in a very narrow bandwidth, and consequently, higher energy peaks. Regulatory agencies test electronic equipment by the amount of peak energy radiated from the equipment. By reducing the peak energy at the fundamental and harmonic frequencies, the equipment under test is able to satisfy agency requirements for EMI. Conventional methods of reducing EMI use shielding, filtering, multilayer PCBs, etc. CY25561 uses the approach of reducing the peak energy in the clock by increasing the clock bandwidth, and lowering the Q. SSCG SSCG uses a patented technology of modulating the clock over a very narrow bandwidth and controlled rate of change, both Document Number: 38-07242 Rev. *K VDD CY25561 50 % Clock frequency = fc = 65 MHz Clock period = Tc =1/65 MHz = 15.4 ns 50 % Tc = 15.4 ns If this clock is applied to the Xin/CLK pin of CY25561, the output clock at pin 4 (SSCLK) sweeps back and forth between two frequencies. These two frequencies, F1 and F2, are used to calculate total amount of spread or bandwidth applied to the reference clock at pin 1. As the clock is making the transition from F1 to F2, the amount of time and sweep waveform play a very important role in the amount of EMI reduction realized from an SSCG clock. The modulation domain analyzer is used to visualize the sweep waveform and sweep period. Figure 4 on page 6 shows the modulation profile of a 65 MHz SSCG clock. Notice that the actual sweep waveform is not a simple sine or sawtooth waveform. Figure 4 on page 6 also shows a scan of the same SSCG clock using a spectrum analyzer. In this scan, you can see a 6.48 dB reduction in the peak RF energy when using the SSCG clock. Page 4 of 13 CY25561 Modulation Rate Spectrum spread clock generators use frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the modulation rate, Tmod. Modulation rates of SSCG clocks are most commonly referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the modulation rate. In some SSCG clock generators, the selected range determines the internal divider count. In other SSCG clocks, the internal divider count is fixed over the operating range of the part. CY25561 has a fixed divider count, as shown in Figure 3. Figure 3. SSCG Clock, Part Number, Fin = 65 MHz Device CY25561 Cdiv 2332 (All Ranges) Example: Device = CY25561 Fin = 65 MHz Range = S1 = 1, S0 = 0 Then; Modulation Rate = Fmod = 65 MHz/2332 = 27.9 kHz. Modulation Profile Spectrum Analyzer Document Number: 38-07242 Rev. *K Page 5 of 13 CY25561 CY25561 Application Schematic Figure 4. Application Schematic VDD C3 0.1 uF 2 90 MHz Reference Clock 1 XIN/CLK VDD SSCLK 8 4 XOUT CY25561 VDD 5 S1 SSCC VSS S0 6 N/C = Logic "M" state 7 3 The schematic in Figure 4 above demonstrates how CY25561 is configured in a typical application. This application is using a 90 MHz reference clock connected to pin 1. Because an external reference clock is used, pin 8 (XOUT) is left unconnected. Figure 4 shows that pin 6 has no connection, which programs the logic “M” state, due to the internal resistor divider network of CY25561. Programming a logic “0” state is as simple as connecting to logic ground, as shown on pin 7. With this configuration, CY25561 produces an SSCG clock that is at a center frequency of 90 MHz. Referring to DC Electrical Characteristics on page 7, range “M, 0” at 90 MHz generates a modulation profile that has a 3.1 percent peak-to-peak spread. Document Number: 38-07242 Rev. *K Page 6 of 13 CY25561 Absolute Maximum Ratings DC input voltage ................................. –0.5 V to VDD + 0.5 V Exceeding maximum ratings [1, 2] may shorten the useful life of the device. User guidelines are not tested. Junction temperature ............................... –40 °C to +140 °C Operating temperature .................................... 0 °C to 70 °C Storage temperature ................................ –65 °C to +150 °C Supply voltage (VDD) ...................................–0.5 V to +6.0 V Static discharge voltage (ESD) .......................... 2,000 V min DC Electrical Characteristics VDD = 3.3 V, TA = 25 °C and CL (Pin 4) = 15 pF, unless otherwise noted. Parameter Description Conditions Min Typ Max Unit VDD Power supply range ±10% 2.97 3.3 3.63 V VINH Input high voltage S0 and S1 only. 0.85 × VDD VDD VDD V VINM Input middle voltage S0 and S1 only. 0.40 × VDD 0.50 × VDD 0.60 × VDD VINL Input low voltage S0 and S1 only. VOH1 Output high voltage VOH2 Output high voltage VOL1 Output low voltage IOH = 6 mA – VOL2 Output low voltage IOH = 20 mA – V 0.0 0.0 0.15 × VDD V IOH = 6 mA 2.4 – – V IOH = 20 mA 2.0 – – V – 0.4 V – 1.2 V Cin1 Input capacitance XIN / CLK (Pin 1) 3 4 5 pF Cin2 Input capacitance XOUT (Pin 8) 6 8 10 pF Cin2 Input capacitance S0, S1, SSCC (Pins 7, 6, 5) 3 4 5 pF IDD1 Power supply current Fin = 65 MHz, CL = 0 – 23 30 mA IDD2 Power supply current Fin = 166 MHz, CL = 0 – 48 60 mA Thermal Resistance Parameter [3] Description θJA Thermal resistance (junction to ambient) θJC Thermal resistance (junction to case) Test Conditions 8-pin SOIC Unit Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 131 °C/W 41 °C/W Notes 1. Operation at any absolute maximum rating is not implied. 2. Single power supply: The voltage on any input or I/O pin cannot exceed the power pine during power-up. 3. These parameters are guaranteed by design and are not tested. Document Number: 38-07242 Rev. *K Page 7 of 13 CY25561 XIN/CLK DC Specifications Parameter VIH(X) VIL(X) Description Input high voltage, XIN Clock Input Conditions Min Max Units F < 100 MHz 80 – % of VDD F < 133 MHz 86 – % of VDD F < 166 MHz 92 – % of VDD – 15 % of VDD Input low voltage, XIN Clock Input Electrical Timing Characteristics VDD = 3.3 V, TA = 25 5 °C and CL = 15 pF, unless otherwise noted. Parameter Description Conditions Min Typ Max Unit ICLKFR Input clock frequency range VDD = 3.3 V 50 – 166 MHz tRISE Clock rise time (Pin 4) SSCLK1 @ 0.4 V–2.4 V 1.1 1.4 1.7 ns tFALL Clock fall time (Pin 4) SSCLK1 @ 0.4 V–2.4 V 1.1 1.4 1.7 ns DTYin Input clock duty cycle XIN / CLK (Pin 1) 30 50 70 % DTYout Output clock duty cycle SSCLK1 (Pin 4) 45 50 55 % CCJ1 Cycle-to-Cycle jitter 50 MHz–100 MHz, (S1 = M, S0 = M) – 150 225 ps CCJ2 Cycle-to-Cycle jitter 100 MHz–166 MHz, (S1 = 1, S0 = M) – 200 300 ps Document Number: 38-07242 Rev. *K Page 8 of 13 CY25561 Ordering Information Part Number Package Type Product Flow CY25561SXC 8-pin SOIC, Pb-free Commercial, 0 C to 70 C CY25561SXCT 8-pin SOIC – Tape and Reel, Pb-free Commercial, 0 C to 70 C Ordering Code Definitions CY 25561 S X C X X = blank or T blank = Tube; T = Tape and Reel Temperature Grade: C = Commercial Pb-free Package Type: S = 8-pin SOIC Base Part Number Company ID: CY = Cypress Document Number: 38-07242 Rev. *K Page 9 of 13 CY25561 Package Drawing and Dimensions Figure 5. 8-pin SOIC (150 Mils) S0815/SZ815/SW815 Package Outline, 51-85066 51-85066 *I Document Number: 38-07242 Rev. *K Page 10 of 13 CY25561 Acronyms Acronym Document Conventions Description Units of Measure EMI Electromagnetic Interference PCB Printed Circuit Board °C degree Celsius PLL Phase-Locked Loop mA milliampere SOIC Small Outline Integrated Circuit ns nanosecond SSC Spread Spectrum Clock % percent SSCC Spread Spectrum Clock Control pF picofarad SSCG Spread Spectrum Clock Generator V volt Document Number: 38-07242 Rev. *K Symbol Unit of Measure Page 11 of 13 CY25561 Document History Page Document Title: CY25561, Spread Spectrum Clock Generator Document Number: 38-07242 Rev. ECN No. Orig. of Change Submission Date ** 115369 OXC 07/05/2002 New data sheet. *A 119443 RGL 10/17/2002 Updated Absolute Maximum Ratings: Updated details corresponding to “Supply Voltage”. Added “DC Input Voltage” and its corresponding details. Added “Junction Temperature” and its corresponding details. Added “Static Discharge Voltage (ESD)” and its corresponding details. *B 122694 RBI 12/27/2002 Updated Absolute Maximum Ratings: Added Note 2 and referred the same note in maximum ratings. *C 2567245 PYG / KVM / AESA 09/16/2008 Updated Ordering Information (Updated part numbers). Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *A to *C. Updated to new template. *D 3187957 CXQ 03/04/2011 Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *C to *D. Completing Sunset Review. *E 3528781 PURU 02/21/2012 Removed Applications. Removed Benefits. Updated Ordering Information: No change in part numbers. Added Ordering Code Definitions. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *D to *E. Added Acronyms and Units of Measure. Updated to new template. Completing Sunset Review. Description of Change *F 3944833 PURU 03/26/2013 Updated Pin Definitions (Replaced “GND” with “VSS” for Name of Pin 3). *G 4198708 CINM 11/21/2013 Added XIN/CLK DC Specifications. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *E to *F. Updated to new template. *H 4586478 AJU 12/03/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *I 4708301 TAVA 03/31/2015 Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *F to *G. Completing Sunset Review. *J 5278942 PSR 05/20/2016 Added Thermal Resistance. Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *G to *H. Updated to new template. *K 6063808 PAWK 02/08/2018 Updated Package Drawing and Dimensions: spec 51-85066 – Changed revision from *H to *I. Updated to new template. Completing Sunset Review. Document Number: 38-07242 Rev. *K Page 12 of 13 CY25561 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Arm® Cortex® Microcontrollers Automotive cypress.com/arm cypress.com/automotive Clocks & Buffers Interface Internet of Things Memory cypress.com/clocks cypress.com/interface cypress.com/iot cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU Cypress Developer Community Community | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support cypress.com/pmic cypress.com/touch cypress.com/usb cypress.com/wireless © Cypress Semiconductor Corporation, 2002-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Document Number: 38-07242 Rev. *K Revised February 8, 2018 Page 13 of 13
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