CY25566SC

CY25566 Spread Spectrum Clock Generator Features • • • • 25- to 200-MHz operating frequency range Wide range of spread selections (9) Accepts clock or crystal inputs Provides four clocks — SSCLK1a — SSCLK1b — SSCLK2 — REFOUT • Low-power dissipation — 3.3V = 70 mW (typical @ 40 MHz, no load) • Center spread modulation • Low cycle-to cycle jitter • 16-pin SOIC package Applications • High-resolution VGA controllers • LCD panels and monitors • Printers and MFPs Benefits • Peak EMI reduction by 8 to 16 dB • Fast time to market • Cost reduction Block Diagram Pin Configuration REFOFF 2 300K 3 REFOUT Xin/ CLK 1 REFERENCE DIVIDER XIN/CLKIN REFOFF 1 2 16 15 XOUT SSCLK2 VSS PD CP Loop Filter REFOUT VDD 3 4 5 6 7 8 CY25566 14 13 S0 12 S1 11 VSS Xout 16 VSS MODULATION CONTROL FEEDBACK DIVIDER vco S2 S3 SSCLK1a 10 SSCC 9 SSCLK1b VDD 4 INPUT DECODER LOGIC VDD VDD DIVIDER & MUX 8 SSCLK1a 9 SSCLK1b /2 15 SSCLK2 VSS 5 VSS 11 VSS 14 20 K 20 K RANGE CONTROL 20 K VSS 20 K VSS 10 SSCC 12 S1 13 S0 6 S2 7 S3 Cypress Semiconductor Corporation Document #: 38-07429 Rev. *B • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised October 26, 2005 CY25566 Pin Description Pin 1 2 3 4 5, 11, 14 6 7 8 9 10 Name XIN/CLKIN REFOFF REFOUT VDD VSS S2 S3 SSCLK1a SSCLK1b SSCC Type I I O P G I I O O I Description Clock or Crystal connection input. Refer to Table 1, Table 2, and Table 3 for input frequency range selection. Input pin enables REFOUT clock at pin 3. REFOFF 400KΩ internal pull-up resistor. Logic “0” enables REFOUT, logic “1” disables REFOUT. Default = disabled. Buffered, non-modulated output clock derived from XIN/CLKIN input frequency. There is a 180° phase shift from XIN to REFOUT. Positive power supply. Bypass to ground with 0.1-µF capacitor. Positive power supply ground. VCO range control. Refer to Table 1, Table 2, and Table 3 for detailed programming information. Has 400-KΩ internal pull-up to VDD. VCO range control. Refer to Table 1, Table 2, and Table 3 for detailed programming information. Has 400-KΩ internal pull-up to VDD. Modulated clock output. Pins 8 and 9 are identical but separate drivers. Modulated clock output. Pins 8 and 9 are identical but separate drivers. Spread Spectrum clock control (enable/disable) function. SSCG function is enabled when input is high and disabled when input is low. Internal 400-KΩ pull-up defaults to modulation ON. Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth selection and tri-level logic programming details. See Figure 2 and Table 1, Table 2, and Table 3. Pin 8 has internal resistor divider network to VDD and VSS. Tri-level logic input control pin used to select frequency and bandwidth. Frequency/bandwidth selection and tri-level logic programming details. See Figure 2 and Table 1, Table 2, and Table 3. Pin 8 has internal resistor divider network to VDD and VSS. Modulated output clock. Frequency of SSCLK2 = SSCLK1a/2. BW% of SSCLK2 is equal to BW% of SSCLK1a/b. Oscillator output pin connected to crystal. Leave this pin unconnected if an external clock drives XIN/CLK. S1. See Table 1, Table 2, and Table 3 for programming details for S2 and S3. The CY25566 will operate over a wide range of frequencies from 25 to 200 MHz. Operation to 200 MHz is possible with the use of dual drivers at pins 8 and 9. With a wide range of selectable bandwidths, the CY25566 is a very flexible low-EMI clock. Modulation can be disabled to provide a four-output conventional clock. The CY25566 is available in a 16-pin SOIC (150-mil.) package with a commercial operating temperature range of 0°C to 70°C. 12 S1 I 13 S0 I 15 16 SSCLK2 XOUT O O General Description The Cypress CY25566 is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing electromagnetic interference (EMI) found in today’s high-speed digital electronic systems. The CY25566 uses a Cypress-proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and frequency modulate the input frequency of the digital clock. By frequency modulating the clock, (SSCLK1a/b and SSCLK2), the measured EMI at the fundamental and harmonic frequencies is greatly reduced. The modulated output frequency is centered on the input frequency. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The CY25566 provides four output clocks: SSCLK1a, SSCLK1b, SSCLK2, and REFOUT. SSCLK1a/b and SSCLK2 are modulated clocks and REFOUT is a buffered copy of the reference clock or oscillator. The CY25566 frequency and spread % ranges are selected by programming S0, S1, S2, and S3 digital inputs. S0 and S1 use three (3) logic states including High (H), Low (L), and Middle (M) to select one of nine available frequency and spread % ranges. Refer to Figure 2 for details on programming three level inputs S0 and Output Clock Architecture The CY25566 provides four separate output clocks: REFOUT, SSCLK1a, SSCLK1b, and SSCLK2 for use in a wide variety of applications. Each clock output is described below in detail. REFOUT REFOUT is a 3.3V CMOS level non-modulated inverted copy of the clock at XIN/CLKIN. As an inverted clock, the output clock at REFOUT is 180° out of phase with the input clock at XIN/CLKIN. Placing a high(1) logic state of REFOFF, pin 2, will disable the REFOUT clock. When REFOUT is disabled, REFOUT, pin 3 is at a low(0) logic state. Document #: 38-07429 Rev. *B Page 2 of 9 CY25566 SSCLK1a/b SSCLK1a and SSCLK1b are spread spectrum clock outputs used for the purpose of reducing EMI in digital systems. SSCLK1a and SSCLK1b can be connected in several different ways to provide flexibility in application designs. Each clock can drive separate nets with a capacitative load up to 15 pF each or connected together to provide drive to a single net with a capacitative load as high as 33 pF. When both clocks are connected together, the CY25566 is capable of driving 3.3V CMOS-compatible clocks to frequencies as high as 200 MHz. If one clock output is not connected to a load, negligible EMI will be generated at the unused pin because there is no current being driven. The frequency and bandwidth of SSCLK1a and SSCLK1b is programmed by the logic states presented to S2 and S3. The frequency multiplication at SSCLK1a and SSCLK1b is either 1X or 2X, controlled by S2 and S3. The modulated output clock SSCLK1 is provided at pins 8 and 9 with each pin having separate but identical drivers. Refer to Figure 1 below. Control Logic Structures The CY25566 has six input control pins for programming VCO range, BW %, Mod ON/OFF and REFOUT ON/OFF. These programmable control pins are described below. REFOFF The output clock REFOUT can be enabled or disabled by controlling the state of REFOFF. When REFOFF is at a logic low(0) state, REFOUT is enabled and the reference clock frequency is present at pin 3. When REFOFF is at a logic high state (1), REFOUT is disabled and is set to a logic low state on pin 3. REFOFF has a 400-KW internal pull-up resistor to VDD. S0 and S1 (Tri-level Inputs) S0 and S1 are used to program the frequency range and bandwidth of the modulated output clocks SSCLK1a/b and SSCLK2. S0 and S1 of the CY25566 are designed to sense three different analog levels. With this tri-level structure, the CY25566 is able to detect 9 different logic states. Refer to tables 5, 6 and 7 for the results of each of these 9 states. The level of each state is defined as follows: Logic State “0” is a voltage that is between 0 and 0.15 × VDDV. Logic State “M” is a voltage between 0.4 × VDD and 0.6 × VDDV. Logic State “1” is a voltage between 0.85 × VDD and VDD. Figure 2 illustrates how to program tri-level logic. CY25566 9 8 3 3 p f. CY25566 9 1 5 p f. 8 1 5 p f. S2 and S3 S2 and S3 are used to program the CY25566 into different frequency ranges and multipliers. The CY25566 operates over a frequency range of 25 to 200 MHz and a 1X or 2X multiplication of the reference frequency. S2 and S3 are binary logic inputs and each has a 400 K W pull-up resistor to VDD. See Table 1, Table 2, and Table 3 for programming details. Figure 1. SSCLK1a/b Driver Configurations SSCLK2 SCLK2 is a Spread Spectrum Clock with a frequency half that of the SSCLK1a clock frequency. When SSCLK1a is programmed to provide a 2.5% modulated clock at 1X times the reference clock, 40 MHz for example, the frequency of SSCLK2 will be 20 MHz with a BW of 2.5%. Note that by programming the frequency of SSCLK1a to 2X, the frequency of SSCLK2 will be 1X times the reference clock frequency. SSCC SSCC is an input control pin that enables or disables SSCG modulation of the output clock at SSCLK1a/b and SSCLK2. Disabling modulation is a method of comparing radiated EMI in a product with SSCG turned on or off. The CY25566 can be used as a conventional low jitter multiple output clock when SSCC is set to low (0). SSCC has a 400-KW internal pull-up resistor. Logic high (1) = Modulation ON, logic low (0) = Modulation OFF. Default is modulation ON. VDD CY25566 S0 = "M" (N/C) S0 13 S1 CY25566 S0 S0 = "1" 13 S1 S1 = "0" (GND) VDD 12 VDD SSCC = "1" 10 CY25566 S0 S0 = "1" 13 VDD S1 = "0" (GND) 12 S1 S1 = "1" 12 SSCC = "1" 10 SSCC = "1" 10 Figure 2. Document #: 38-07429 Rev. *B Page 3 of 9 CY25566 Modulation Rate Spread Spectrum clock generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (Fmax) and minimum frequency of the clock (Fmin) determine this band of frequencies. The time required to transition from Fmin to Fmax and back to Fmin is the period of the Modulation Rate, Tmod. Modulation Rates of SSCG clocks are generally referred to in terms of frequency or Fmod = 1/Tmod. The input clock frequency, Fin, and the internal divider count, Cdiv, determine the Modulation Rate. The CY25566 utilizes two different modulation rate dividers, depending on the range selected on S2 and S3 digital control inputs. Refer to the example below. S3, S2 0,0 0,1 1,0 1,1 CDiv 1166 1166 2332 N/A Output Frequency 1X 2X 1X N/A The CY25566 has three frequency groups to select from. Each combination of frequency and bandwidth can be selected by programming the input control lines, S0–S3, to the proper logic state. Group 1 is the 1X low-frequency range and operates from 25 to 100 MHz. Group 2 is the 1X high-frequency range and operates from 50 to 200 MHz. Group 3 is the 2X low frequency range and operates from 25 to 50 MHz and 50 to 100 MHz output. Example: Device = CY25566 Fin = 65 MHz Range = S3 = 0, S2 = 1, S0 = 0 Then: modulation rate = Fmod = 65 MHz/1166 = 55.7 kHz Modulation Profile Spectrum Analyzer Figure 3. SSCG Clock, CY25566, 65 MHz Document #: 38-07429 Rev. *B Page 4 of 9 CY25566 Table 1. Frequency and Bandwidth Selection Chart (Group 1)(Low Frequency (1x) Selection Chart) 25–50 MHz (Low Range) XIN/CLK (MHz) 25–35 35–40 40–45 45–50 XIN/CLK (MHz) 50–60 60–70 70–80 80–100 S1 = M S0 = M 4.3 3.9 3.7 3.4 S1 = 1 S0 = M 2.9 2.8 2.6 2.4 S1 = M S0 = 0 3.8 3.5 3.3 3.1 S1 = 0 S0 = 1 2.1 2.0 1.8 1.7 S1 = 1 S0 = 0 3.4 3.1 2.8 2.6 S1 = 1 S0 = 1 1.5 1.4 1.3 1.2 S1 = 0 S0 = 0 2.9 2.5 2.4 2.2 S1 = M S0 = 1 1.2 1.1 1.1 1.0 S1 = 0 S0 = M 2.8 2.4 2.3 2.1 S3 S2 0 0 50–100 MHz (High Range) S3 S2 0 0 Table 2. Frequency and Bandwidth Selection Chart (Group 2)(High Frequency (1x) Selection Chart) 50–100 MHz (Low Range) XIN/CLK (MHz) 50–60 60–70 70–80 80–100 XIN/CLK (MHz) 100–120 120–130 130–140 140–150 150–160 160–170 170–180 180–190 190–200 S1 = M S0 = M 4.2 4.0 3.8 3.5 S1 = 1 S0 = M 3.0 2.7 2.6 2.6 2.5 2.4 2.4 2.3 2.3 S1 = M S0 =0 3.8 3.6 3.4 3.1 S1 = 0 S0 = 1 2.4 2.1 2.0 2.0 1.8 1.8 1.8 1.7 1.6 S1 = 1 S0 = 0 3.2 3.1 2.9 2.7 S1 = 1 S0 = 1 1.6 1.4 1.3 1.3 1.2 1.2 1.2 1.1 1.1 S1 = 0 S0 = 0 2.8 2.6 2.5 2.2 S1 = M S0 = 1 1.3 1.1 1.1 1.1 1.0 1.0 1.0 0.9 0.9 S1 = 0 S0 = M 2.7 2.5 2.4 2.1 S3 S2 100–200 MHz (High Range) 1 0 S3 S2 1 0 Table 3. Frequency and Bandwidth Selection Chart (Group 3)(Low Frequency (2x) Selection Chart) 25–50 MHz (Low Range, 2X) XIN/CLK (MHz) 25–35 35–40 40–45 45–50 SSCLK1 (MHz) 50-70 70-80 80-90 90-100 S1 = M S0 = M 4.0 3.8 3.5 3.3 S1 = M S0 = 0 3.5 3.3 3.1 2.9 S1 = 1 S0 = 0 3.0 2.9 2.7 2.5 S1 = 0 S0 = 0 2.6 2.4 2.2 2.1 S1 = 0 S0 = M 2.5 2.3 2.1 2.0 S3 S2 0 1 Document #: 38-07429 Rev. *B Page 5 of 9 CY25566 Application Schematic In this example, the CY25566 is being driven by a 75-MHz reference clock. S0 = 0 and S1 = 0 are programmed to select a BW of 2.5%. (Refer to Table 1 and 2.) S2 = 0 and S3 = 1 are programmed to select the Group 2 range. VDD 0.1 uF 4 1 XIN/CLKIN VDD REFOUT 16 XOUT SSCLK2 15 SSCLK2 3 REFOUT VDD = 3.30 VDC. SSCLK1a = 75 MHz @ 2.5% center spread modulation. SSCLK1b = 75 MHz @ 2.5% center spread modulation. SSCLK 2 = 37.5 MHz @ 2.5% center spread modulation. REFOUT = 37.5 MHz non-modulated clock. 75 MHz Clock source CY25566 2 VDD 10 7 6 12 13 SSCC S3 S2 S1 S0 REFOFF SSCLK1a 8 SSCLK1a SSCLK1b 9 SSCLK1b VSS VSS 11 VSS 14 5 Figure 4. Application Schematic Document #: 38-07429 Rev. *B Page 6 of 9 CY25566 Absolute Maximum Ratings[1, 2] Supply Voltage (VDD: .......................................................+6V Operating Temperature: ...................................... 0°C to 70°C Storage Temperature .................................. –65°C to +150°C Table 4. DC Electrical Characteristics VDD = 3.3V, Temp. = 25°C, unless otherwise noted Parameter VDD VINH VINM VINL VOH1 VOH2 VOL1 VOL2 Cin1 Cin2 Cin2 IDD1 IDD1 IDD2 IDD2 Description Power Supply Range Input High Voltage Input Middle Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Output Low Voltage Input Capacitance Input Capacitance Input Capacitance Power Supply Current Power Supply Current Power Supply Current Power Supply Current ±10% S0 and S1 only. S0 and S1 only. S0 and S1 only. IOH = 6 ma, SSCLKa IOH = 20 ma, SSCLKb IOH = 6 ma, SSCLKa IOH = 20 ma, SSCLKb Xin/CLK (Pin 1) Xout (Pin 8) All input pins except 1. FIN = 40 MHz,15 pF@all outputs FIN = 40 MHz, No Load FIN = 165 MHz,15 pF@all outputs FIN = 165 MHz, No Load 3 6 3 4 8 4 27 21 68 48 Conditions Min. 2.97 0.85VDD 0.40VDD 0.0 2.4 2.0 0.4 1.2 5 10 5 32 28 80 60 Typ. 3.3 VDD 0.50VDD 0.0 Max. 3.63 VDD 0.60VDD 0.15VDD Unit V V V V V V V V pF pF pF mA mA mA mA Table 5. Electrical Timing Characteristics VDD = 3.3V, T = 25°C and CL = 15 pF, unless otherwise noted. Rise/Fall @ 0.4–2.4V, Duty@1.5V Parameter ICLKFR tRISE(a) tFALL(a) tRISE(a+b) tFALL(a+b) tRISE(a+b) tFALL(a+b) tRISE(REF) tFALL(REF) DTYin DTYout CCJ1 CCJ2 REFOUT Description Clock Rise Time Clock Fall Time Clock Rise Time Clock Fall Time Clock Rise Time Clock Fall Time Clock Rise Time Clock Fall Time Input Clock Duty Cycle Output Clock Duty Cycle Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter Refout Frequency Range Conditions SSCLK1a or SSCLK1b, Freq = 100 MHz SSCLK1a or SSCLK1b, Freq = 100 MHz SSCLK1(a+b), CL = 33 pF, 100 MHz SSCLK1(a+b), CL = 33 pF, 100 MHz SSCLK1(a+b), CL = 33 pF, 200 MHz SSCLK1(a+b), CL = 33 pF, 200 MHz REFOUT, Pin 3, CL = 15 pF, 50 MHz REFOUT, Pin 3, CL = 15 pF, 50 MHz XIN/CLK (Pin) SSCLK1a/b (Pin 8 and 9) F = 100 MHz, SSCLK1a/b CL = 33 pF F = 200 MHz, SSCLK1a/b CL = 33 pF CL = 15 pF 25 Min. 25 1.0 1.0 1.2 1.2 1.1 1.1 1.0 1.0 30 45 1.3 1.3 1.5 1.5 1.4 1.4 1.3 1.3 50 50 300 500 Typ. Max 200 1.6 1.6 1.8 1.8 1.7 1.7 1.6 1.6 70 55 400 600 108 Unit MHz ns ns ns ns ns ns ns ns % % ps ps MHz Input Clock Frequency Range Non-crystal, 3.0V Pk–Pk ext. source Note: 1. Operation at any Absolute Maximum Rating is not implied. 2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Document #: 38-07429 Rev. *B Page 7 of 9 CY25566 Ordering Information Part Number CY25566SC CY25566SCT 16-pin SOIC 16-pin SOIC–Tape and Reel Package Type Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Package Drawing and Dimensions 16 Lead (150 Mil) SOIC 8 1 16-Lead (150-Mil) SOIC S16.15 PIN 1 ID DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012 0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197] PACKAGE WEIGHT 0.15gms PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16 0.386[9.804] 0.393[9.982] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 51-85068-*B All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07429 Rev. *B Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY25566 Document Title:CY25566 Spread Spectrum Clock Generator Document Number: 38-07429 Rev. ** *A *B ECN No. 115771 122705 404070 Issue Date 07/01/02 12/30/02 See ECN Orig. of Change OXC RBI RGL New Data Sheet Added power up requirements to maximum ratings information. Minor Change: Typo error on table 1, column 2 , S0 = 0 (not M) Description of Change Document #: 38-07429 Rev. *B Page 9 of 9