CY25568

CY25568 Spread Spectrum Clock Generator Features ■ ■ ■ ■ ■ ■ ■ Applications ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 4 to 32 MHz Input frequency range 4 to 128 MHz Output frequency range accepts clock, crystal and resonator Inputs 1x, 2x and 4x frequency multiplication Non-modulated reference frequency output Center and down spread modulation Low power dissipation ❐ 3.3 V = 52 mW-typ at 6 MHz ❐ 3.3 V = 60 mW-typ at 12 MHz ❐ 3.3 V = 72 mW-typ at 24 MHz Power-down mode Low cycle-to cycle jitter ❐ 8 MHz = 195 ps-typ ❐ 16 MHz = 175 ps-typ ❐ 32 MHz = 100 ps-typ Available in 16-pin (150-mil.) SOIC package Printers and MFPs LCD panels and monitors Digital copiers PDAs Automotive CD-ROM, VCD and DVD Networking, LAN/WAN Scanners Modems Embedded digital systems ■ ■ Benefits ■ ■ ■ Peak EMI reduction by 8 to 16dB Fast time to market Cost reduction ■ Logic Block Diagram 300K 7 REFOUT XIN 1 8pF REFERENCE DIVIDER PD and CP LF XOUT 16 8pF MODULATION CONTROL VDD VDD VSS VSS 13 VCO COUNTER VCO 6 12 SSCLK1 SSCLK2 SSCLK3 3 2 INPUT DECODER LOGIC 11 4 5 1 5 1 4 1 0 DIVIDER and MUX 9 8 FRSEL S1 SO D1 DO PD# Cypress Semiconductor Corporation Document Number: 38-07111 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 18, 2011 CY25568 Contents Pinouts .............................................................................. 2 Pin Definitions .................................................................. 2 General Description ......................................................... 2 Absolute Maximum Ratings ............................................ 3 DC Electrical Characteristics .......................................... 3 Timing Electrical Characteristics .................................... 3 Input Frequency Range and Selection ........................... 4 Output Clocks .............................................................. 4 REFOUT ...................................................................... 4 SSCLK1, 2 and 3 ......................................................... 4 Spread% Selection ........................................................... 5 3-Level Digital Inputs ................................................... 5 Power Down (PD#) ...................................................... 6 Modulation Rate .......................................................... 6 Characteristic Curves ...................................................... 7 SSCG Profiles ............................................................. 8 Application Schematic ..................................................... 9 Ordering Code Definitions ........................................... 9 Package Diagram ............................................................ 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document Number: 38-07111 Rev. *D Page 2 of 14 CY25568 Pinouts Figure 1. CY25568 - 16 Pin SOIC XIN/CLKIN VSS VSS S1 S0 SSCLK1 REFOUT SSCK3 1 2 3 4 5 6 7 8 16 15 14 XOUT D1 D0 VDD VDD FRSEL PD# SSCLK2 CY25568 13 12 11 10 9 Pin Definitions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Function Xin/CLK VSS VSS S1 S0 SSCLK1 REFOUT SSCLK3 SSCLK2 PD# FRSEL VDD VDD D0 D1 XOUT Clock, crystal or ceramic resonator input pin Power supply ground. Power supply ground. Digital Spread% control pin 3-Level input (H-M-L). Default= M. Digital Spread% control pin 3-Level input (H-M-L). Default= M. Output clock. Refer to Table 2 on page 5 for frequency programmability. Reference clock output. The same frequency as Xin/CLK input. Output clock. Refer to Table 2 on page 5 for frequency programmability. Output clock. Refer to Table 2 on page 5 for frequency programmability. Power-down control Internally pulled to VDD, Default= High. Input frequency range selection digital control input 3-Level input (H-M-L). Default= M. Positive power supply. Positive power supply. 3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 5. Default= M. 3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 5. Default= M. Crystal or ceramic resonator output pin the input frequency with spread spectrum. A separate non-modulated reference clock is also provided. The use of 2x or 4x frequency multiplication eliminates the need for higher order crystals and allows the user to generate up to 128 MHz spread spectrum clock (SSC) by using only first order crystals. This reduces the cost while improving the system clock accuracy, performance and complexity center spread or down spread frequency modulation can be selected by the user based on 4 discrete values of Spread% for each spread mode with the option of a non-spread mode for system test and verification purposes. The CY25568 is available in a 16 pin SOIC (150-mil.) package with a commercial operating temperature range of 0 to 70 C. Contact Cypress for availability of –25 to +85 C industrial temperature range operation. Refer to CY25811/12/14 products for 8-pin SOIC package versions of the CY25568. Description General Description The Cypress CY25568 is a spread spectrum clock generator (SSCG) IC used for the purpose of reducing electro magnetic interference (EMI) found in today's high-speed digital electronic systems. The CY25568 uses a Cypress proprietary phase-locked loop (PLL) and spread spectrum clock (SSC) technology to synthesize and modulate the frequency of the digital clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The CY25568 input frequency range is 4 to 32 MHz and accepts clock, crystal, and ceramic resonator inputs. The output clocks can be programmed to produce 1x, 2x, and 4x multiplication of Document Number: 38-07111 Rev. *D Page 3 of 14 CY25568 Absolute Maximum Ratings [1] Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Supply voltage (VDD): ................................................. +5.5 V Input voltage relative to VDD: ............................... VDD+0.3 V Note: Operation at any Absolute Maximum Rating is not implied. Input voltage relative to VSS: ............................... VSS–0.3 V Operating temperature: ........................................ 0 to 70 c storage Temperature: .................................. –65 to +150 C DC Electrical Characteristics Test Conditions: VDD=3.3 V, T=25, unless otherwise noted Symbol VDD VINH VINM VINL VINH1 VINL1 VOH1 VOH2 VOL1 VOL2 Cin1 Cin2 IDD1 IDD2 IDD3 Parameter Power supply range Input high voltage Input middle voltage Input low voltage Input high voltage Input low voltage Output high voltage Output high voltage Output low voltage Output low voltage Input capacitance Input capacitance Power supply current Power supply current Power supply current Min 2.90 0.85 VDD 0.40VDD 0.0 2.0 2.4 2.0 6.0 3.5 Typ. 3.3 VDD 0.50VDD 0.0 7.5 4.5 13.0 28.0 300 Max 3.60 VDD 0.60VDD 0.15VDD 0.8 0.4 1.2 9.0 6.0 16.0 32.0 400 Unit V V V V V V V V V V pF pF mA mA ìA S0,S1,D0,D1 and FRSEL Inputs S0,S1,D0,D1 and FRSEL Inputs S0,S1,D0,D1 and FRSEL Inputs PD# input only PD# input only IOH = 4 ma, all output clocks IOH = 6 ma, all output clocks IOL = 4 ma, all output clocks IOL = 10 ma, all output clocks Xin (Pin 1) and Xout (Pin 16) All digital inputs Fin=4 MHz, no load (refer to Figure 4 on page 8) Fin=32 MHz, no load (refer to Figure 4 on page 8) PD#=GND Conditions Timing Electrical Characteristics Test Conditions: VDD=3.3 V, T=25 C, CL=15pF. Rise/Fall time at 0.4 and 2.4 V, duty cycle at 1.5 V Symbol trise1 tfall1 trise2 tfall2 trise3 tfall3 CDCin CCJ1 CCJ2 Parameter Clock rise time Clock fall time Clock rise time Clock fall time Clock rise time Clock fall time Input clock duty cycle Cycle-to-cycle jitter Cycle-to-cycle jitter Min 4 2.4 2.4 1.2 1.2 2.4 2.4 20 45 3.2 3.2 1.6 1.6 3.2 3.2 50 50 195 170 Typ. Max 32 4.0 4.0 2.0 2.0 4.0 4.0 80 55 260 225 Unit MHz ns ns ns ns ns ns % % ps ps Conditions Clock, crystal or ceramic resonator input SSCLK1,2, and 3, all cases when 1x or 2x scaling selected, when 4x if FRSEL=1 or 0 SSCLK1,2, and 3, all cases when 1x or 2x scaling selected, when 4x if FRSEL=1 or 0 SSCLK2, and 3, only when 4x scaling is selected and FRSEL=M SSCLK2, and 3, only when 4x scaling is selected and FRSEL=M REFOUT only REFOUT only XIN/CLK (Pin 1) SSCLK1,2 and 3 Fin=8 MHz (refer to Figure 4 on page 8) Fin=16 MHz (refer to Figure 4 on page 8) ICLKFR Input frequency range CDCout Output clock duty cycle Notes 1. Single Power Supply: The voltage on any input or IO pin cannot exceed the power pin during power-up. Document Number: 38-07111 Rev. *D Page 4 of 14 CY25568 Timing Electrical Characteristics Test Conditions: VDD=3.3 V, T=25 C, CL=15pF. Rise/Fall time at 0.4 and 2.4 V, duty cycle at 1.5 V CCJ3 Cycle-to-cycle jitter 100 150 ps Fin=32 MHz (refer to Figure 4A) Input Frequency Range and Selection The CY25568 input frequency range is 4 to 32 MHz. This range is divided into 3 segments and controlled by 3-Level FRSEL pin as given in Table 1. Table 1. Input Frequency Selection FRSEL 0 1 M INPUT FREQUENCY RANGE 4.0 to 8.0 MHz 8.0 to 16.0 MHz 16.0 to 32.0 MHz Output Clocks The CY25568 provides 4 separate output clocks, REFOUT, SSCLK1, SSCLK2 and SSCLK3, for use in a wide variety of applications.Each clock output is described in detail. REFOUT REFOUT is a 3.3 volt CMOS level non-modulated copy of the clock at XIN/CLKIN. SSCLK1, 2 and 3 SSCLK1, SSCLK2 and SSCLK3 are Spread Spectrum clock outputs used for the purpose of reducing EMI in digital systems. Each clock can drive separate nets with a capacitive load of up to 20 pF. The frequency function of these clock outputs are selected by using 3-Level D0 and D1 digital inputs and are given in Table 2. Table 2. Output Clocks Function Selection D0 0 0 0 M M M 1 1 1 D1 0 M 1 0 M 1 0 M 1 REFOUT REF REF REF REF REF REF REF REF REF SSCLK1 REF 1x REF REF REF REF REF 1x 1x SSCLK2 1x 2x 2x 1x REF 2x 4x 2x 2x SSCLK3 1x 2x 2x 2x REF 4x 4x 4x 4x REF is the same non-modulated frequency as the input clock. 1x, 2x, or 4x are modulated and multiplied (in the case of 2x and 4x) frequency of the input clock. Document Number: 38-07111 Rev. *D Page 5 of 14 CY25568 Spread % Selection The CY25568 provides Center-Spread, Down-Spread and No-Spread functions. These functions and the amount of Spread% are selected by using 3-Level S0 and S1 digital inputs and are given in Table 3. Table 3. Spread% Selection XIN (MHz) FRSEL S1=0 S0=0 CENTER (%) 4-5 5-6 6-7 7-8 8-10 10-12 12-14 14-16 16-20 20-24 24-28 28-32 0 0 0 0 1 1 1 1 M M M M +/–1.4 +/–1.3 +/–1.2 +/–1.1 +/–1.4 +/–1.3 +/–1.2 +/–1.1 +/–1.4 +/–1.3 +/–1.2 +/–1.1 S1=0 S0=M CENTER (%) +/–1.2 +/–1.1 +/–0.9 +/–0.9 +/–1.2 +/–1.1 +/–0.9 +/–0.9 +/–1.2 +/–1.1 +/–0.9 +/–0.9 S1=0 S0=1 CENTER (%) +/–0.6 +/–0.5 +/–0.5 +/–0.4 +/–0.6 +/–0.5 +/–0.5 +/–0.4 +/–0.6 +/–0.5 +/–0.5 +/–0.4 S1=M S0=0 CENTER (%) +/–0.5 +/–0.4 +/–0.4 +/–0.3 +/–0.5 +/–0.4 +/–0.4 +/–0.3 +/–0.5 +/–0.4 +/–0.4 +/–0.3 S1=1 S0=1 DOWN (%) –3.0 –2.7 –2.5 –2.3 –3.0 –2.7 –2.5 –2.3 –3.0 –2.7 –2.5 –2.3 S1=1 S0=0 DOWN (%) –2.2 –1.9 –1.8 –1.7 –2.2 –1.9 –1.8 –1.7 –2.2 –1.9 –1.8 –1.7 S1=M S0=1 DOWN (%) –1.9 –.7 –1.5 –1.4 –1.9 –1.7 –1.5 –1.4 –1.9 –1.7 –1.5 –1.4 S1=1 S0=M DOWN (%) –0.7 –0.6 –0.6 –0.5 –0.7 –0.6 –0.6 –0.5 –0.7 –0.6 –0.6 –0.5 S1=M S0=M NO SPREAD 0 0 0 0 0 0 0 0 0 0 0 0 3-Level Digital Inputs Figure 2. 3-Level Logic LOGIC LOW (0) LOGIC MIDDLE (M) LOGIC HIGH (H) VDD DO, D1, S0, S1 and FRSEL to GND D0, D1, S0, S1 and FRSEL UNCONNECTED D0, D1, S0, S1 and FRSEL to VDD GND S0, S1, D0, D1, and FRSEL digital inputs of the CY25568 are designed to sense 3 different logic levels designated as High - 1, Low- 0 and Middle- M. With this 3-Level digital input logic, the CY25568 is able to detect 9 different logic states in the case of (S0, S1) and (D0, D1) logic pairs and 3 different logic states in the case of FRSEL. S0, S1, D0, D1, and FRSEL pins include an on chip 20K (10K /10K) resistor divider. No external application resistors are needed to implement the 3-Level logic levels as shown in the following: Logic State 0 = 3-Level logic pin connected to GND. Logic State M = 3-Level logic pin left floating (no connection). Logic State 1 = 3-Level logic pin connected to VDD. Figure 2 illustrates how to implement 3-Level Logic. Document Number: 38-07111 Rev. *D Page 6 of 14 CY25568 Power-down (PD#) CY25568 includes a Power-down (PD#, Pin 10) function. This input uses standard 2-Level CMOS logic and is internally pulled up to VDD (HIGH). Connect this pin to GND if power is to be turned off. Modulation Rate Spread Spectrum Clock Generators use frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rate of SSCG clocks are generally referred to in terms of frequency or fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the modulation rate. In the case of CY25568, the (spread spectrum) modulation rate is given by the following formula: fmod = fin/DR Where; fmod is the modulation rate, fin is the Input Frequency and DR is the divider ratio as given in Table 4. Notice that Input frequency range is set by FRSEL. Table 4. Modulation Rate FRSEL 0 1 M INPUT FREQUENCY RANGE (MHz) 4 to 8 8 to 16 16 to 32 DIVIDER RATIO (DR) 128 256 512 Document Number: 38-07111 Rev. *D Page 7 of 14 CY25568 Characteristic Curves The following curves demonstrate the characteristic behavior of the CY25568 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in tables “DC Electrical Characteristics” on page 4 and “Timing Electrical Characteristics” on page 4. Figure 3. Jitter vs. Input Frequency (No Load) 600 Figure 5. IDD vs. Frequency (FRSEL = 0, 1, M) 30 28 500 26 24 IDD (mA ) FRSEL = M 16 - 32 MHz 400 CCJ (ps) 22 20 18 300 FRSEL = 1 8 - 16 MHz 200 16 14 12 100 FRSEL = 0 4 - 8 MHz 0 4 8 12 16 20 24 28 32 10 4 4.5 5 5.5 6 6.5 7 7.5 8 Input Frequency (M z) H Fre qu ency (M Hz) n o load, no rm alize d to FRSEL = 0, (4 - 8 MHz) . Figure 4. Bandwidth% vs. Temperature 2.75 6.0 MH z 32.0MHz Figure 6. Bandwidth% vs. VDD 3 2.9 2.8 2.7 2.5 2.25 BW (%) BW % 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 2.8 2.9 3 3.1 3.2 3.3 4.0 MHz 2 8.0 MHz 1.75 -40 -25 -10 5 20 35 50 65 80 95 110 125 3.4 3.5 3.6 3.7 Temp(C) VDD (volts) Document Number: 38-07111 Rev. *D Page 8 of 14 CY25568 SSCG Profiles The CY25568 uses a non-linear frequency profile as shown in Figure 7. The use of Cypress proprietary “optimized” frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems. Figure 7. Spread Spectrum Profiles (Frequency versus Time)   Xin = 6.0 MHz S1, S0 = 0 SSCLK1 = 6.0 MHz D1, D0 = 1 Xin = 24.0 MHz S1, S0 = 0 SSCLK1 = 24.0 MHz D1, D0 = 1 Xin = 12.0 MHz S1, S0 = 0 SSCLK1 = 48.0 MHz D1, D0 = 1 Xin = 24.0 MHz S1, S0 = 0 SSCLK1 = 96.0 MHz D1, D0 = 1 Document Number: 38-07111 Rev. *D Page 9 of 14 CY25568 Application Schematic Figure 8. Application Schematic Ordering Information Part No. Pb-free CY25568SXC CY25568SXCT 16 Pin SOIC 16 Pin SOIC – Tape and Reel 0 to 70 C 0 to 70 C Package Operating Temperature Range Ordering Code Definitions CY 25568 S X C T T = Tape and Reel; blank = Tube Temperature Range: C = Commercial Pb-free Package: S = 16-pin SOIC Base part number Company ID: CY = Cypress Document Number: 38-07111 Rev. *D Page 10 of 14 CY25568 Package Diagram Figure 9. 16-Pin (150-Mil) SOIC 51-85068 *C Document Number: 38-07111 Rev. *D Page 11 of 14 CY25568 Acronyms Acronym DVD EMI I/O LAN LCD PLL SOIC SSC SSCG VCD WAN Description digital versatile/video disc electromagnetic interference input/output local area network liquid crystal display phase-locked loop small-outline integrated circuit spread spectrum clock spread spectrum clock generator video compact disc wide area network Document Conventions Units of Measure Symbol % °C dB mA MHz mm ms mW ns pF ps V  W percent degree Celsius decibel milliamperes Megahertz millimeter milliseconds milliwatts nanoseconds picofarad picoseconds volts ohms watts Unit of Measure Document Number: 38-07111 Rev. *D Page 12 of 14 CY25568 Document History Page Document Title: CY25568 Spread Spectrum Clock Generator Document Number: 38-07111 Rev. ** *A *B *C ECN 107515 108182 122682 2658020 Orig. of Change NDP NDP RBI KVM/PYRS Submission Date 06/14/01 07/03/01 12/21/02 02/16/09 Description of Change Convert from IMI to Cypress Delete “Junction Temp” in Absolute maximum Ratings (page 4) Added power-up requirements to Absolute Maximum Ratings information. Updated Ordering Information Table with Pb-free part numbers. Deleted the table “16 Pin SOIC Outline Dimensions (150 mil)” Updated template Update to latest template Added Ordering Code Definitions Updated Package Diagram Added Acronyms Added Units of Measure Added Contents *D 3319217 BASH 07/08/18 Document Number: 38-07111 Rev. *D Page 13 of 14 CY25568 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2001-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07111 Rev. *D Revised July 18, 2011 Page 14 of 14