CY25568
Spread Spectrum Clock Generator
Spread Spectrum Clock Generator
Features
■
LCD panels and monitors
■
Digital copiers
■
PDAs
■
4 to 32 MHz Input frequency range
■
4 to 128 MHz Output frequency range
■
accepts clock, crystal and resonator Inputs
■
Automotive
■
1x, 2x and 4x frequency multiplication
■
CD-ROM, VCD and DVD
■
Non-modulated reference frequency output
■
Networking, LAN/WAN
■
Center and down spread modulation
■
Scanners
■
Low power dissipation
❐ 3.3 V = 52 mW-typ at 6 MHz
❐ 3.3 V = 60 mW-typ at 12 MHz
❐ 3.3 V = 72 mW-typ at 24 MHz
■
Modems
■
Embedded digital systems
■
Power-down mode
■
Peak EMI reduction by 8 to 16dB
■
Low cycle-to cycle jitter
❐ 8 MHz = 195 ps-typ
❐ 16 MHz = 175 ps-typ
❐ 32 MHz = 100 ps-typ
■
Fast time to market
■
Cost reduction
■
Benefits
Functional Description
Available in 16-pin (150-mil.) SOIC package
For a complete list of related documentation, click here.
Applications
■
Printers and MFPs
Logic Block Diagram
300K
XIN
1
8pF
XOUT
REFERENCE
DIVIDER
PD and CP
LF
MODULATION
CONTROL
VCO
COUNTER
VCO
7
REFOUT
6
SSCLK1
16
8pF
VDD
13
VDD
12
VSS
3
VSS
2
11
FRSEL
Cypress Semiconductor Corporation
Document Number: 38-07111 Rev. *H
DIVIDER
and
MUX
INPUT
DECODER LOGIC
•
4
5
1
5
1
4
9
SSCLK2
8
SSCLK3
1
0
S1 SO D1 DO PD#
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2017
CY25568
Contents
Pin Configuration ............................................................. 3
Pin Definitions .................................................................. 3
Functional Overview ........................................................ 3
Absolute Maximum Ratings ............................................ 4
DC Electrical Characteristics .......................................... 4
Thermal Resistance .......................................................... 4
Timing Electrical Characteristics .................................... 5
Input Frequency Range and Selection ........................... 5
Output Clocks .............................................................. 6
REFOUT ...................................................................... 6
SSCLK1, 2 and 3 ......................................................... 6
Spread% Selection ........................................................... 7
3-Level Digital Inputs ................................................... 7
Power-down (PD#) ...................................................... 8
Modulation Rate .......................................................... 8
Characteristic Curves ...................................................... 9
Document Number: 38-07111 Rev. *H
SSCG Profiles ........................................................... 10
Application Schematic ................................................... 11
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagram ............................................................ 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ....................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Page 2 of 15
CY25568
Pin Configuration
Figure 1. 16-pin SOIC pinout
CY25568
XIN/CLKIN
1
16
VSS
2
15
D1
VSS
3
14
D0
XOUT
S1
4
13
VDD
S0
5
12
VDD
CY25568
SSCLK1
6
11
FRSEL
REFOUT
7
10
PD#
SSCK3
8
9
SSCLK2
Pin Definitions
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Function
Xin/CLK
VSS
VSS
S1
S0
SSCLK1
REFOUT
SSCLK3
SSCLK2
PD#
FRSEL
VDD
VDD
D0
D1
XOUT
Description
Clock, crystal or ceramic resonator input pin
Power supply ground.
Power supply ground.
Digital Spread% control pin 3-Level input (H-M-L). Default = M.
Digital Spread% control pin 3-Level input (H-M-L). Default = M.
Output clock. Refer to Table 2 on page 6 for frequency programmability.
Reference clock output. The same frequency as Xin/CLK input.
Output clock. Refer to Table 2 on page 6 for frequency programmability.
Output clock. Refer to Table 2 on page 6 for frequency programmability.
Power-down control Internally pulled to VDD, Default = High.
Input frequency range selection digital control input 3-Level input (H-M-L). Default = M.
Positive power supply.
Positive power supply.
3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 6. Default = M.
3-Level (H-M-L) Digital output clock scaling control. Refer to Table 2 on page 6. Default = M.
Crystal or ceramic resonator output pin
Functional Overview
the input frequency with spread spectrum. A separate
non-modulated reference clock is also provided.
The Cypress CY25568 is a spread spectrum clock generator
(SSCG) IC used for the purpose of reducing electro magnetic
interference (EMI) found in today's high-speed digital electronic
systems.
The use of 2x or 4x frequency multiplication eliminates the need
for higher order crystals and allows the user to generate up to
128 MHz spread spectrum clock (SSC) by using only first order
crystals. This reduces the cost while improving the system clock
accuracy, performance and complexity.
The CY25568 uses a Cypress proprietary phase-locked loop
(PLL) and spread spectrum clock (SSC) technology to
synthesize and modulate the frequency of the digital clock. By
frequency modulating the clock, the measured EMI at the
fundamental and harmonic frequencies is greatly reduced.
This reduction in radiated energy can significantly reduce the
cost of complying with regulatory agency requirements and
improve time to market without degrading system performance.
The CY25568 input frequency range is 4 to 32 MHz and accepts
clock, crystal, and ceramic resonator inputs. The output clocks
can be programmed to produce 1x, 2x, and 4x multiplication of
Document Number: 38-07111 Rev. *H
The center spread or down spread frequency modulation can be
selected by the user based on 4 discrete values of Spread% for
each spread mode with the option of a non-spread mode for
system test and verification purposes.
The CY25568 is available in a 16-pin SOIC (150-mil.) package
with a commercial operating temperature range of 0 to 70 C.
Contact Cypress for availability of –25 to +85 C industrial
temperature range operation. Refer to CY25811/12/14 products
for 8-pin SOIC package versions of the CY25568.
Page 3 of 15
CY25568
Input voltage relative to VDD: ............................. VDD + 0.3 V
Input voltage relative to VSS: ............................. VSS – 0.3 V
Absolute Maximum Ratings
Exceeding maximum ratings [1] may shorten the useful life of the
device. User guidelines are not tested.
Operating temperature: .........................................0 to 70C
Supply voltage (VDD): ................................................. +5.5 V
storage Temperature: .............................. –65 C to +150C
Note: Operation at any Absolute Maximum Rating is not implied.
DC Electrical Characteristics
Test Conditions: VDD = 3.3 V, T = 25 °C, unless otherwise noted
Symbol
Parameter
Min
Typ
Max
Unit
2.90
3.3
3.60
V
Input high voltage
0.85 × VDD
VDD
VDD
V
S0,S1,D0,D1 and FRSEL Inputs
Input middle voltage
0.40 × VDD 0.50 × VDD 0.60 × VDD
V
S0,S1,D0,D1 and FRSEL Inputs
VDD
Power supply range
VINH
VINM
Conditions
VINL
Input low voltage
0.0
0.0
0.15 × VDD
V
S0,S1,D0,D1 and FRSEL Inputs
VINH1
Input high voltage
2.0
–
–
V
PD# input only
VINL1
Input low voltage
–
–
0.8
V
PD# input only
VOH1
Output high voltage
2.4
–
–
V
IOH = 4 mA, all output clocks
VOH2
Output high voltage
2.0
–
–
V
IOH = 6 mA, all output clocks
VOL1
Output low voltage
–
–
0.4
V
IOL = 4 mA, all output clocks
VOL2
Output low voltage
–
–
1.2
V
IOL = 10 mA, all output clocks
Cin1
Input capacitance
6.0
7.5
9.0
pF
Xin (Pin 1) and Xout (Pin 16)
Cin2
Input capacitance
3.5
4.5
6.0
pF
All digital inputs
IDD1
Power supply current
–
13.0
16.0
mA
Fin = 4 MHz, no load (refer to Figure 4
on page 9)
IDD2
Power supply current
–
28.0
32.0
mA
Fin = 32 MHz, no load
(refer to Figure 4 on page 9)
IDD3
Power supply current
–
300
400
µA
PD# = GND
Thermal Resistance
Parameter [2]
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Test Conditions
16-pin SOIC
Unit
Test conditions follow standard test methods and
procedures for measuring thermal impedance, in
accordance with EIA/JESD51.
115
°C/W
45
°C/W
Notes
1. Single Power Supply: The voltage on any input or IO pin cannot exceed the power pin during power-up.
2. These parameters are guaranteed by design and are not tested.
Document Number: 38-07111 Rev. *H
Page 4 of 15
CY25568
Timing Electrical Characteristics
Test Conditions: VDD = 3.3 V, T = 25 °C, CL = 15 pF. Rise/Fall time at 0.4 and 2.4 V, duty cycle at 1.5 V
Symbol
Parameter
Min
Typ
4
Max
32
Unit
Conditions
ICLKFR
Input frequency range
MHz Clock, crystal or ceramic resonator
input
trise1
Clock rise time
2.4
3.2
4.0
ns
SSCLK1, 2, and 3, all cases when 1x
or 2x scaling selected, when 4x if
FRSEL = 1 or 0
tfall1
Clock fall time
2.4
3.2
4.0
ns
SSCLK1,2, and 3, all cases when 1x or
2x scaling selected, when 4x if
FRSEL = 1 or 0
trise2
Clock rise time
1.2
1.6
2.0
ns
SSCLK2, and 3, only when 4x scaling
is selected and FRSEL = M
tfall2
Clock fall time
1.2
1.6
2.0
ns
SSCLK2, and 3, only when 4x scaling
is selected and FRSEL = M
trise3
Clock rise time
2.4
3.2
4.0
ns
REFOUT only
tfall3
Clock fall time
2.4
3.2
4.0
ns
REFOUT only
CDCin
Input clock duty cycle
20
50
80
%
XIN/CLK (Pin 1)
CDCout
Output clock duty cycle
45
50
55
%
SSCLK1, 2 and 3
CCJ1
Cycle-to-cycle jitter
-
195
260
ps
Fin = 8 MHz
(refer to Figure 4 on page 9)
CCJ2
Cycle-to-cycle jitter
-
170
225
ps
Fin = 16 MHz
(refer to Figure 4 on page 9)
CCJ3
Cycle-to-cycle jitter
-
100
150
ps
Fin = 32 MHz (refer to Figure 4A)
Input Frequency Range and Selection
The CY25568 input frequency range is 4 to 32 MHz. This range is divided into 3 segments and controlled by 3-Level FRSEL pin as
given in Table 1.
Table 1. Input Frequency Selection
FRSEL
INPUT FREQUENCY RANGE
0
4.0 to 8.0 MHz
1
8.0 to 16.0 MHz
M
16.0 to 32.0 MHz
Document Number: 38-07111 Rev. *H
Page 5 of 15
CY25568
Output Clocks
The CY25568 provides 4 separate output clocks, REFOUT, SSCLK1, SSCLK2 and SSCLK3, for use in a wide variety of
applications.Each clock output is described in detail.
REFOUT
REFOUT is a 3.3 volt CMOS level non-modulated copy of the clock at XIN/CLKIN.
SSCLK1, 2 and 3
SSCLK1, SSCLK2 and SSCLK3 are Spread Spectrum clock outputs used for the purpose of reducing EMI in digital systems. Each
clock can drive separate nets with a capacitive load of up to 20 pF.
The frequency function of these clock outputs are selected by using 3-Level D0 and D1 digital inputs and are given in Table 2.
Table 2. Output Clocks Function Selection
D0
D1
REFOUT
SSCLK1
SSCLK2
SSCLK3
0
0
REF
REF
1x
1x
0
M
REF
1x
2x
2x
0
1
REF
REF
2x
2x
M
0
REF
REF
1x
2x
M
M
REF
REF
REF
REF
M
1
REF
REF
2x
4x
1
0
REF
REF
4x
4x
1
M
REF
1x
2x
4x
1
1
REF
1x
2x
4x
REF is the same non-modulated frequency as the input clock.
1x, 2x, or 4x are modulated and multiplied (in the case of 2x and 4x) frequency of the input clock.
Document Number: 38-07111 Rev. *H
Page 6 of 15
CY25568
Spread% Selection
The CY25568 provides Center-Spread, Down-Spread and No-Spread functions. These functions and the amount of Spread% are
selected by using 3-Level S0 and S1 digital inputs and are given in Table 3.
Table 3. Spread% Selection
XIN
(MHz)
S1=0
S0=0
S1=0
S0=M
S1=0
S0=1
S1=M
S0=0
S1=1
S0=1
S1=1
S0=0
S1=M
S0=1
S1=1
S0=M
S1=M
S0=M
CENTER
(%)
CENTER
(%)
CENTER
(%)
CENTER
(%)
DOWN
(%)
DOWN
(%)
DOWN
(%)
DOWN
(%)
NO
SPREAD
0
+/–1.4
+/–1.2
+/–0.6
+/–0.5
–3.0
–2.2
–1.9
–0.7
0
5-6
0
+/–1.3
+/–1.1
+/–0.5
+/–0.4
–2.7
–1.9
–.7
–0.6
0
6-7
0
+/–1.2
+/–0.9
+/–0.5
+/–0.4
–2.5
–1.8
–1.5
–0.6
0
4-5
FRSEL
7-8
0
+/–1.1
+/–0.9
+/–0.4
+/–0.3
–2.3
–1.7
–1.4
–0.5
0
8-10
1
+/–1.4
+/–1.2
+/–0.6
+/–0.5
–3.0
–2.2
–1.9
–0.7
0
10-12
1
+/–1.3
+/–1.1
+/–0.5
+/–0.4
–2.7
–1.9
–1.7
–0.6
0
12-14
1
+/–1.2
+/–0.9
+/–0.5
+/–0.4
–2.5
–1.8
–1.5
–0.6
0
14-16
1
+/–1.1
+/–0.9
+/–0.4
+/–0.3
–2.3
–1.7
–1.4
–0.5
0
16-20
M
+/–1.4
+/–1.2
+/–0.6
+/–0.5
–3.0
–2.2
–1.9
–0.7
0
20-24
M
+/–1.3
+/–1.1
+/–0.5
+/–0.4
–2.7
–1.9
–1.7
–0.6
0
24-28
M
+/–1.2
+/–0.9
+/–0.5
+/–0.4
–2.5
–1.8
–1.5
–0.6
0
28-32
M
+/–1.1
+/–0.9
+/–0.4
+/–0.3
–2.3
–1.7
–1.4
–0.5
0
3-Level Digital Inputs
Figure 2. 3-Level Logic
LOGIC
LOW (0)
LOGIC
MIDDLE (M)
LOGIC
HIGH (H)
VDD
D0, D1, S0, S1
and
FRSEL
UNCONNECTED
DO, D1, S0, S1
and
FRSEL
to GND
D0, D1, S0, S1
and
FRSEL
to VDD
GND
S0, S1, D0, D1, and FRSEL digital inputs of the CY25568 are designed to sense 3 different logic levels designated as High - 1,
Low- 0 and Middle - M. With this 3-Level digital input logic, the CY25568 is able to detect 9 different logic states in the case of (S0,
S1) and (D0, D1) logic pairs and 3 different logic states in the case of FRSEL.
S0, S1, D0, D1, and FRSEL pins include an on chip 20K (10K /10K) resistor divider. No external application resistors are needed to
implement the 3-Level logic levels as shown in the following:
Logic State 0 = 3-Level logic pin connected to GND.
Logic State M = 3-Level logic pin left floating (no connection).
Logic State 1 = 3-Level logic pin connected to VDD.
Figure 2 illustrates how to implement 3-Level Logic.
Document Number: 38-07111 Rev. *H
Page 7 of 15
CY25568
Power-down (PD#)
CY25568 includes a Power-down (PD#, Pin 10) function. This input uses standard 2-Level CMOS logic and is internally pulled up to
VDD (HIGH). Connect this pin to GND if power is to be turned off.
Modulation Rate
Spread Spectrum Clock Generators use frequency modulation (FM) to distribute energy over a specific band of frequencies. The
maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time
required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rate of SSCG
clocks are generally referred to in terms of frequency or fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider determine the modulation rate.
In the case of CY25568, the (spread spectrum) modulation rate is given by the following formula: fmod = fin/DR
Where; fmod is the modulation rate, fin is the Input Frequency and DR is the divider ratio as given in Table 4. Notice that Input
frequency range is set by FRSEL.
Table 4. Modulation Rate
FRSEL
INPUT FREQUENCY RANGE (MHz)
DIVIDER RATIO (DR)
0
4 to 8
128
1
8 to 16
256
M
16 to 32
512
Document Number: 38-07111 Rev. *H
Page 8 of 15
CY25568
Characteristic Curves
The following curves demonstrate the characteristic behavior of the CY25568 when tested over a number of environmental and
application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in tables
DC Electrical Characteristics on page 4 and Timing Electrical Characteristics on page 5.
Figure 3. Jitter vs. Input Frequency (No Load)
Figure 5. IDD vs. Frequency (FRSEL = 0, 1, M)
30
600
28
500
24
IDD (mA )
400
CCJ (ps)
FRSEL = M
16 - 32 MHz
26
300
22
FRSEL = 1
8 - 16 MHz
20
18
200
16
FRSEL = 0
4 - 8 MHz
14
100
12
0
10
4
8
12
16
20
24
28
32
4
4.5
Input Frequency (MHz)
2.75
BW (%)
BW %
2.5
2.25
2
-10
5
20
35
50
Temp(C)
Document Number: 38-07111 Rev. *H
65
6
6.5
7
7.5
8
3
2.9
2.8
2.7
6.0 MHz
32.0MHz
-25
5.5
Figure 6. Bandwidth% vs. VDD
Figure 4. Bandwidth% vs. Temperature
1.75
-40
5
Fre qu ency (M Hz) n o load, no rm alize d to FRSEL = 0, (4 - 8 MHz) .
80
95
110
125
2.6
2.5
4.0 MHz
2.4
2.3
2.2
2.1
8.0 MHz
2
1.9
1.8
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
VDD (volts)
Page 9 of 15
CY25568
SSCG Profiles
The CY25568 uses a non-linear frequency profile as shown in Figure 7. The use of Cypress proprietary “optimized” frequency profile
maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in
electronic systems.
Figure 7. Spread Spectrum Profiles (Frequency versus Time)
Xin = 6.0 MHz
SSCLK1 = 6.0 MHz
Xin = 24.0 MHz
SSCLK1 = 24.0 MHz
S1, S0 = 0
D1, D0 = 1
S1, S0 = 0
D1, D0 = 1
Xin = 12.0 MHz
SSCLK1 = 48.0 MHz
Xin = 24.0 MHz
SSCLK1 = 96.0 MHz
S1, S0 = 0
D1, D0 = 1
S1, S0 = 0
D1, D0 = 1
Document Number: 38-07111 Rev. *H
Page 10 of 15
CY25568
Application Schematic
Figure 8. Application Schematic
Ordering Information
Part No.
Package
Operating Temperature Range
Pb-free
CY25568SXC
16-pin SOIC
Commercial, 0 °C to 70 °C
CY25568SXCT
16-pin SOIC – Tape and Reel
Commercial, 0 °C to 70 °C
Ordering Code Definitions
CY 25568 S
X
C
T
T = Tape and Reel; blank = Tube
Temperature Range: C = Commercial
Pb-free
Package: S = 16-pin SOIC
Base Part Number
Company ID: CY = Cypress
Document Number: 38-07111 Rev. *H
Page 11 of 15
CY25568
Package Diagram
Figure 9. 16-pin SOIC (150 Mils) S16.15/SZ16.15 Package Outline, 51-85068
51-85068 *E
Document Number: 38-07111 Rev. *H
Page 12 of 15
CY25568
Acronyms
Acronym
Document Conventions
Description
Units of Measure
DVD
digital versatile/video disc
EMI
Electromagnetic Interference
%
percent
I/O
input/output
°C
degree Celsius
LAN
local area network
dB
decibel
LCD
liquid crystal display
MHz
megahertz
PLL
phase-locked loop
mA
milliampere
SOIC
small-outline integrated circuit
mm
millimeter
SSC
spread spectrum clock
ms
millisecond
SSCG
spread spectrum clock generator
mW
milliwatt
VCD
video compact disc
ns
nanosecond
WAN
wide area network
ohm
pF
picofarad
ps
picosecond
V
volt
W
watt
Document Number: 38-07111 Rev. *H
Symbol
Unit of Measure
Page 13 of 15
CY25568
Document History Page
Document Title: CY25568, Spread Spectrum Clock Generator
Document Number: 38-07111
Rev.
ECN
Orig. of
Change
Submission
Date
**
107515
NDP
06/14/2001
Convert from IMI to Cypress.
*A
108182
NDP
07/03/2001
Updated Absolute Maximum Ratings:
Removed “Junction Temperature (10-sec. soldering)”.
*B
122682
RBI
12/21/2002
Updated Absolute Maximum Ratings:
Added Note 1 and referred the same note in maximum ratings.
*C
2658020
KVM /
PYRS
02/16/2009
Updated Ordering Information:
Updated part numbers.
Updated Package Diagram:
Deleted the table “16 Pin SOIC Outline Dimensions (150 mil)”.
Updated to new template.
*D
3319217
BASH
07/08/2011
Added Ordering Code Definitions under Ordering Information.
Updated Package Diagram.
Added Acronyms and Units of Measure.
Updated to new template.
*E
4468746
TAVA
08/07/2014
Updated Package Diagram:
spec 51-85068 – Changed revision from *C to *E.
Updated to new template.
Completing Sunset Review.
*F
4586478
TAVA
12/03/2014
Updated Functional Description:
Added “For a complete list of related documentation, click here.” at the end.
*G
5281153
PSR
05/23/2016
Added Thermal Resistance.
Updated to new template.
Completing Sunset Review.
*H
5981734
AESATP12
12/01/2017
Updated logo and copyright.
Document Number: 38-07111 Rev. *H
Description of Change
Page 14 of 15
CY25568
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2001-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC (“Cypress”). This document,
including any software or firmware included or referenced in this document (“Software”), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
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Document Number: 38-07111 Rev. *H
Revised December 1, 2017
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