CY25702LXCZZZT

CY25702 Programmable High-Frequency Crystal Oscillator (XO) Features • • • • • • • • • • Programmable High-frequency Crystal Oscillator (XO) Wide operating output clock frequency range of 1–166 MHz Integrated phase-locked loop (PLL) 85 ps typical cycle-to-cycle Jitter with CLK = 133 MHz 3.3V operation Output Enable and Power-down functions Package available in 4-Pin Ceramic LCC SMD Pb-free package Industrial Temperature from –40°C to 85°C For SSCG functionality refer to CY25701 data sheet Benefits • Internal PLL to generate up to 166 MHz output • Suitable for most PC, consumer, and networking applications • Application compatibility in standard and low-power systems • CY25701 can be used as a direct replacement without any PCB modification if spread spectrum clock (SSC) is required for EMI reduction. • In-house programming of samples and prototype quantities is available using CY3672 programming kit and CY3724 socket adapters. Production quantities are available through Cypress’s value-added distribution partners or by using third-party programmers from BP Microsystems, HiLo Systems, and others. Logic Block Diagram RFB Pin Configuration CY25702 4-pin Ceramic SMD PLL 4 VDD 3 CLK CXIN PROGRAMMABLE CONFIGURATION CXOUT OUTPUT DIVIDERS and MUX 3 CLK OE/PD# 1 VSS 2 1 OE/PD# 4 VDD 2 VSS Cypress Semiconductor Corporation Document #: 38-07721 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 07, 2006 CY25702 Pin Definition Pin 1 2 3 4 OE/PD# VSS CLK VDD Name Description Output Enable pin: Active HIGH. If OE = 1, CLK is enabled. Power Down pin: Active LOW. If PD# = 0, Power Down is enabled. Power supply ground. Clock output. 3.3V power supply. Table 1. Programming Data Requirement Pin Function Pin Name Pin# Units Program Value Output Frequency CLK 3 MHz ENTER DATA Output Enable/Power Down OE/PD# 1 N/A ENTER DATA Functional Description The CY25702 is a programmable high-frequency Crystal Oscillator (XO) that uses a Cypress proprietary PLL to synthesize the frequency of the embedded input crystal. The CY25702 uses a programmable configuration memory array to synthesize output frequency. The frequency CLK output can be programmed from 1 MHz to 166 MHz. The CY25702 is available in a 4-pin ceramic SMD package with an operating temperature range of –40 to 85°C. Output Frequency, CLK Output (CLK, pin 3) The frequency at the CLK output is produced by synthesizing the embedded crystal oscillator frequency input. The range of the synthesized clock is from 1 MHz to 166 MHz. Output Enable or Power Down (OE/PD#, pin 1) Pin 1 can be programmed as either output enable (OE) or Power Down (PD#). Absolute Maximum Rating Supply Voltage (VDD)......................................–0.5V to +7.0V DC Input Voltage ................................... –0.5V to VDD + 0.5V Storage Temperature (Non-condensing) ...... –55°C to 100°C Junction Temperature .................................. –40°C to 125°C Data Retention @ Tj = 125°C................................> 10 years Package Power Dissipation...................................... 350 mW Programming Description Field/Factory-Programmable CY25702 Field/Factory programming is available for samples and manufacturing by Cypress and its distributors. All requests must be submitted to the local Cypress Field Application Engineer (FAE) or sales representative. Once the request has been processed, you will receive a new part number, samples, and data sheet with the programmed values. This part number will be used for additional sample requests and production orders. Additional information on the CY25702 can be obtained from the Cypress web site at www.cypress.com. Operating Conditions Parameter VDD TA TA CLOAD FCLK TPU Supply Voltage Ambient Temperature (Commercial) Ambient Temperature (Industrial) Max. Load Capacitance @ pin 3 CLK output frequency, CLOAD = 15 pF Power-up time for VDD to reach minimum specified voltage (power ramp must be monotonic) Description Min. 3.00 –20 –40 – 1 0.05 Typ. 3.30 – – – – – Max. 3.60 70 85 15 166 500 Unit V °C °C pF MHz ms Document #: 38-07721 Rev. *C Page 2 of 6 CY25702 DC Electrical Characteristics Parameter IOH IOL VIH VIL IIH IIL IOZ CIN[1] IVDD Δf/f Description Output High Current (pin 3) Output Low Current (pin 3) Input High Voltage (pin 1) Input Low Voltage (pin 1) Input High Current (pin 1) Input Low Current (pin 1) Output Leakage Current (pin 3) Input Capacitance (pin 1) Supply Current Initial Accuracy at Room Temp. Condition VOH = VDD – 0.5, VDD = 3.3V (source) VOL = 0.5, VDD = 3.3V (sink) CMOS levels, 70% of VDD CMOS levels, 30% of VDD Vin = VDD Vin = VSS Three-state output, OE = 0 Pin 1, or OE VDD = 3.3V, CLK = 1 to 166 MHz, CLOAD = 0, OE = VDD TA = 25°C, 3.3V Min. 10 10 0.7VDD – – – –10 – – –25 –25 –12 –5 Typ. 12 12 – – – – – 5 – – – – – Max. – – VDD 0.3VDD 10 10 10 7 50 25 25 12 5 Unit mA mA V V μA μA μA pF mA ppm ppm ppm ppm Freq. Stability over Temp. Range TA = –20°C to 70°C, 3.3V Freq. Stability over Voltage Range 3.0 to 3.6V Aging TA = 25°C, First year AC Electrical Characteristics[1] Parameter DC tR tF TCCJ1[2] Description Output Duty Cycle Output Rise Time Output Fall Time Cycle-to-Cycle Jitter CLK (Pin 3) Condition CLK, Measured at VDD/2 20%–80% of VDD, CL=15 pF 20%–80% of VDD, CL=15 pF CLK > 133 MHz, Measured at VDD/2 25 MHz < CLK < 133 MHz, Measured at VDD/2 CLK < 25 MHz, Measured at VDD/2 Min. 45 – – – – – – – – Typ. 50 – – 85 215 – 150 150 – Max. 55 2.7 2.7 200 400 500 350 350 10 Unit % ns ns ps ps ps ns ns ms TOE1 TOE2 TLOCK Output Disable Time (pin1 = OE) Output Enable Time (pin1 = OE) PLL Lock Time Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous) Time for CLK to reach valid frequency Note 1. Guaranteed by characterization, not 100% tested. 2. Jitter is configuration dependent. Actual jitter is dependent on output frequencies, spread percentage, temperature, and output load. For more information, refer to the application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at http://www.cypress.com/clock/appnotes.html, or contact your local Cypress Field Application Engineer. Document #: 38-07721 Rev. *C Page 3 of 6 CY25702 Application Circuit Figure 1. Application Circuit Diagram Pow er 4 VDD 0 .1 µ F 3 CLK C Y25702 O E /P D # 1 VSS 2 VDD Switching Waveforms Figure 2. Duty Cycle Waveform Cycle Timing (DC = t1A/t1B) t1A t1B CLK Figure 3. Output Rise/Fall Time Waveform VDD CLK 0V Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values. Figure 4. Output Enable/Disable Timing Waveforms VDD 0V VIL VIH OUTPUT ENABLE TOE2 CLK (Asynchronous) TOE1 High Impedance Document #: 38-07721 Rev. *C Page 4 of 6 CY25702 Ordering Information Part Number Lead-free (Pb-free) CY25702FLXCT[3] CY25702FLXIT[3] CY25702LXCZZZT[4] CY25702LXIZZZT[4] 4-Lead Ceramic LCC SMD -Tape and Reel 4-Lead Ceramic LCC SMD -Tape and Reel 4-Lead Ceramic LCC SMD -Tape and Reel 4-Lead Ceramic LCC SMD -Tape and Reel Commercial, –20° to 70°C Industrial, –40° to 85°C Commercial, –20° to 70°C Industrial, –40° to 85°C Package Description Product Flow Actual Marking[5] CY25702FLX* Marketing Part Number (CY25702) F=Field Programmable CY25702LX* Marketing Part Number (CY25702) L = LCC CY L X Pin 1 mark L = LCC X = Pb free 2 * Temp 5 7 0 2 F C X Pin 1 mark X = Pb free Y * Temp 2 z 5 z 7 z 0 2L Y WW YWW = Date Code (Year & WW) Y WW zzz = Programmable Dash Code YWW = Date Code (Year & WW) Package Drawings and Dimensions Figure 5. 4-Lead (5.0x3.2 mm) Ceramic LCC LZ04A Dimensions in MM General Tolerance: ± 0.15MM Kyocera dwg ref KD-VA5G08 Package Weight ~ 0.12 grams 0.50 1.30 Max SIDE VIEW 5.0 0.80 1.20 3.2 #3 #2 #4 #1 2.90 2.50 TOP VIEW BOTTOM VIEW 001-02743-*B All product and company names mentioned in this document are the trademarks of their respective holders. Notes 3. “FLX” suffix is used for products programmed in field by Cypress Distributors. 4. “ZZZ” denotes the assigned product dash number. This number will be assigned by factory after the output frequency programming data is received from the customer. 5. Temp can be C (Commercial) or I (Industrial). Document #: 38-07721 Rev. *C Page 5 of 6 © Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY25702 Document History Page Document Title: CY25702 Programmable High-Frequency Crystal Oscillator (XO) Document Number: 38-07721 REV. ** *A *B *C ECN NO. 296081 333298 390406 595857 Issue Date See ECN See ECN See ECN See ECN Orig. of Change RGL RGL RGL RGL New data sheet Description of Change Added Jitter Specifications Corrected the Ordering Information table to match the DevMaster Removed CY25702FXC and CY25702XCZZZ Complete data sheet rewrite Document #: 38-07721 Rev. *C Page 6 of 6