CY25819
Spread Spectrum Clock Generator
Spread Spectrum Clock Generator
Features
■ ■ ■ ■ ■ ■ ■
Applications
■ ■ ■ ■ ■ ■ ■ ■ ■ ■
8- to 32-MHz input frequency range CY25819: 16 MHz to 32 MHz Separate modulated and unmodulated clocks Accepts clock, crystal, and resonator inputs Down spread modulation Power-down function Low-power dissipation ❐ CY25819 = 36 mW typ at 16 MHz ❐ CY25819 = 63 mW typ at 32 MHz Low cycle-to-cycle jitter ❐ SSCLK = 250 ps typ ❐ REFOUT = 275 ps typ Available in 8-pin (150 mil) SOIC package
Printers and MFPs LCD panels and notebook PCs Digital copiers PDAs Automotive CD-ROM, VCD, and DVD Networking and LAN/WAN Scanners Modems Embedded digital systems
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■
Benefits
■ ■ ■
Peak electromagnetic interference (EMI) reduction by 8 dB to 16 dB Fast time to market Cost reduction
Block Diagram
300K
XIN/CLKIN 1 XOUT 8
REFERENCE DIVIDER
PD and CP
LF
MODULATION CONTROL
VDD
7
VCO COUNTER
VCO
VSS 2
INPUT DECODER
3 6
DIVIDER and MUX
4 5
SSCLK REFCLK
S0 PD#
Cypress Semiconductor Corporation Document #: 38-07362 Rev. *D
•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600 Revised May 10, 2011
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CY25819
Contents
Pin Configuration ............................................................. 3 Pin Description ................................................................. 3 Overview ............................................................................ 4 Input Frequency Range and Selection ........................... 4 Spread% Selection ........................................................... 4 3-Level Digital Inputs ....................................................... 5 Modulation Rate ................................................................ 5 Maximum Ratings ............................................................. 6 DC Electrical Characteristics .......................................... 6 Timing Electrical Characteristics .................................... 6 Characteristics Curves .................................................... 7 SSCG Profiles ................................................................... 8 Application Schematic ..................................................... 9 Ordering Information ........................................................ 9 Ordering Code Definitions ........................................... 9 Package Drawing and Dimensions ............................... 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13
Document #: 38-07362 Rev. *D
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CY25819
Pin Configuration
8-pin SOIC
XIN/CLKIN 1 Vss 2 S0 3 SSCLK 4
8 XOUT
CY25818 CY25819
7 Vdd 6 PD# 5 REFCLK
Pin Description
Pin
1 2 3 4 5 6 7 8
Name
XIN/CLK Vss S0 SSCLK REFCLK PD# Vdd XOUT Clock, Crystal, or Ceramic Resonator Input Pin. Power Supply Ground.
Description
Digital Spread% Control Pin. 3-Level input (H-M-L). Default = M. Modulated Spread Spectrum Output Clock. The output frequency is referenced to input frequency. Refer to Table 2 on page 4 for the amount of modulation (Spread%). Unmodulated Reference Clock Output. The unmodulated output frequency is the same as the input frequency. Power Down Control Pin. Default = H (Vdd).
Positive Power Supply.
Clock, Crystal, or Ceramic Resonator Output Pin. Leave this pin unconnected if an external clock is used at XIN pin.
Document #: 38-07362 Rev. *D
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CY25819
Overview
The Cypress CY25819 products are Spread Spectrum Clock Generator (SSCG) ICs used for the purpose of reducing EMI found in today’s high-speed digital electronic systems. The devices use a Cypress proprietary phase-locked loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements and improve time to market without degrading system performance. The input frequency range is 8–16 MHz for the CY25818 and 16–32 MHz for the CY25819. Both products accept external clock, crystal, or ceramic resonator inputs. The CY25819 provide separate modulated (SSCLK) and unmodulated reference (REFCLK) clock outputs which are the same frequency as the input clock frequency. Down spread frequency modulation can be selected by the user, based on three discrete values of Spread%. A separate power down function is also provided. The CY25819 products are available in an 8-pin SOIC (150-mil) package with a commercial operating temperature range of 0–70 C. Contact Cypress for availability of –40 to +85 C industrial temperature range operation or TSSOP package versions.
Input Frequency Range and Selection
CY25819 input frequency range is 8–32 MHz. This range is divided into two segments, as given in Table 1.
Table 1. Input and Output Frequency Selection Product CY25819 Input/Output Frequency Range 16–32 MHz
Spread% Selection
CY25818/19 SSCG products provide Down-Spread frequency modulation. The amount of Spread% is selected by using 3-Level S0 digital input. Spread% values are given in Table 2.
Table 2. Spread% Selection XIN (MHz)
16–20 20–24 24–28 28–32
Product
CY25819 CY25819 CY25819 CY25819
S0 = 1 Down (%) –3.0 –2.7 –2.5 –2.3
S0 = 0 Down (%) –2.2 –1.9 –1.8 –1.7
S0 = M Down (%) –0.7 –0.6 –0.6 –0.5
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CY25819
3-Level Digital Inputs
S0 digital input is designed to sense three logic levels designated as HIGH “1”, LOW “0”, and MIDDLE “M”. With this 3-Level digital input logic, the 3-Level logic is able to detect three different logic levels. The S0 pin includes an on-chip 20K (10K/10K) resistor divider. No external application resistors are needed to implement 3-Level logic, as follows. Logic Level “0”: 3-Level logic pin connected to GND. Logic Level “M”: 3-Level logic pin left floating (no connection). Logic Level “1”: 3-Level logic pin connected to Vdd. Figure 1 illustrates how to implement 3-Level Logic.
Modulation Rate
Spread Spectrum Clock Generators utilize frequency modulation (FM) to distribute energy over a specific band of frequencies. The maximum frequency of the clock (fmax) and minimum frequency of the clock (fmin) determine this band of frequencies. The time required to transition from fmin to fmax and back to fmin is the period of the Modulation Rate, Tmod. The Modulation Rates of SSCG clocks are generally referred to in terms of frequency, and fmod = 1/Tmod. The input clock frequency, fin, and the internal divider determine the Modulation Rate. In the case of CY25819 devices, the (Spread Spectrum) Modulation Rate, fmod, is given by the following formula: fmod = fIN/DR
L O G IC H IG H (H )
VDD
Figure 1. 3-Level Logic
L O G IC L O W (0 ) L O G IC M ID D L E (M )
where fmod is the Modulation Rate, fIN is the Input Frequency, and DR is the Divider Ratio, as given in Table 3.
S0 to V S S
S0 UNCO NNECTED
S0 to V D D
VSS
Table 3. Modulation Rate Divider Ratios Product
CY25818 CY25819
Input Frequency Range
8–16 MHz 16–32 MHz
Divider Ratio (DR)
256 512
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CY25819
Maximum Ratings[1, 2]
Supply Voltage (Vdd): .................................................. +5.5 V Input Voltage Relative to Vdd: .............................Vdd + 0.3 V Input Voltage Relative to Vss:.............................. Vss + 0.3 V Operating Temperature:.................................. 0 C to +70 C Storage Temperature: ............................... –65 C to +150 C
DC Electrical Characteristics
Vdd = 3.3 V ± 10%, TA = 0 C to +70 C and CL = 15 pF (unless otherwise noted)
Parameter
Vdd VINH VINM VINL VOH1 VOH2 VOL1 VOL2 CIN1 CIN2 IDD1 IDD3 IDD4
Description
Power Supply Range Input HIGH Voltage Input MIDDLE Voltage Input LOW Voltage Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input Capacitance Input Capacitance Power Supply Current Power Supply Current Power Supply Current S0 Input S0 Input S0 Input
Conditions
Min
2.97 0.85 Vdd 0.40 Vdd 0.0 2.4 2.0 – – 6.0 3.5 – – –
Typ
3.3 Vdd 0.50 Vdd 0.0 – – – – 7.5 4.5 10.0 19.0 150
Max
3.63 Vdd 0.60 Vdd 0.15 Vdd – – 0.4 1.2 9.0 6.0 12.5 23.0 250
Unit
V V V V V V V V pF pF mA mA mA
IOH = 4 mA, SSCLK and REFCLK IOH = 6 mA, SSCLK and REFCLK IOL = 4 mA, SSCLK Output IOL = 10 mA, SSCLK Output XIN (Pin 1) and XOUT (Pin 8) All Digital Inputs FIN = 8 MHz, no load FIN = 32 MHz, no load PD# = Vss
Timing Electrical Characteristics
Vdd = 3.3 V ± 10%, TA = 0 C to +70 C and CL = 15 pF (unless otherwise noted)
Parameter
ICLKFR1 ICLKFR2 trise1 tfall1 CDCin CDCout CCJss CCJref
Description
Input Frequency Range CY25818 Input Frequency Range CY25819 Clock Rise Time Clock Fall Time Input Clock Duty Cycle Cycle-to-Cycle Jitter Cycle-to-Cycle Jitter
Conditions
Min
8 16 2.0 2.0 20 45 – –
Typ
– – 3.0 3.0 50 50 250 275
Max
16 32 4.0 4.0 80 55 350 375
Unit
MHz MHz ns ns % % ps ps
SSCLK and REFCLK, 0.4V to 2.4V SSCLK and REFCLK, 0.4V to 2.4V XIN SSCLK; FIN = FOUT = 8–32 MHz REFCLK; FIN = FOUT = 8–32 MHz
Output Clock Duty Cycle SSCLK and REFCLK @ 1.5V
Notes 1. Single Power Supply: The voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. Operation at any Absolute Maximum Rating is not implied.
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CY25819
Characteristics Curves
The following curves demonstrate the characteristic behavior of the CY25819 when tested over a number of environmental and application specific parameters. These are typical performance curves and are not meant to replace any parameter specified in DC Electrical Characteristics on page 6 and Timing Electrical Characteristics on page 6.
IDD(mA)
Figure 4. IDD (mA) vs. Frequency (MHz)
20 19 18 17
C Y 2 5 8 18 8 - 16 M H z
C Y 2 5 8 19 16 - 3 2 M H z
Figure 2. CCJ (ps) vs. Frequency (MHz)
300 290 280 270
16 15 14
REFCLK CY25819 REFCLK CY25818
13 12 11 10
CCJ (ps)
260 250 240 230
8
12
16
20
24
28
32
SSCLK CY25819
F r e q ue nc y ( M H z )
SSCLK CY25818
220 210 200 8 12 16 20 24 28 32
Figure 5. Bandwidth% vs. Vdd
3.1 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 2.8
32.0 MHz
Frequency (MHz)
CY25818@8.0 MHz
Figure 3. Bandwidth% vs. Temperature
2.75
B.W % BW (%)
CY25819@32 MHz
2.5
12 MHz
B.WBW % %
2.25
2.9
3
3.1
3.2
VDD (volts)
3.3
3.4
3.5
3.6
3.7
2
1.75 -40 -25 -10 5 20 35 50 65 80 95 110 125
Temp (C)
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CY25819
SSCG Profiles
CY25819 SSCG products use a non-linear “optimized” frequency profile as shown in Figure 6. The use of Cypress proprietary “optimized” frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in additional EMI reduction in electronic systems.
Figure 6. CY25819 Spread Spectrum Profile (Frequency vs. Time)[3]
Note 3. Xin = 32.0 MHz; S0 = 1; SSCLK = 32.0 MHz; BW = –2.15%.
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CY25819
Application Schematic
Figure 7. Typical Application Schematic
Vdd C3 0.1 uF
7 C2 1
14.3 MHz or 27.0 MHz
XIN
Vdd SSCLK
4 5 14.3 MHz (CY25818) 27.0 MHz (CY25819)
27 pF C3
8
XOUT
R EFCLK
27 pF
CY25818 CY25819
6
PD# S0
3
V ss
2
Ordering Information
Part Number Pb-Free
CY25819SXC CY25819SXCT 8-pin SOIC 8-pin SOIC–Tape and Reel Commercial, 0C to 70C Commercial, 0C to 70C
Package Type
Product Flow
Ordering Code Definitions
CY 25819 S X C T
T = Tape and Reel; blank = Tube Temperature Range: C = Commercial Pb-free Package: S = 8-pin SOIC Base part number Company ID: CY = Cypress
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CY25819
Package Drawing and Dimensions
Figure 8. 8-pin SOIC 150 Mils S08.15/SZ08.15
51-85066 *D
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CY25819
Acronyms
Acronym
DVD EMI I/O LAN LCD PLL SOIC SSC SSCG VCD WAN
Document Conventions
Description
Units of Measure
Symbol
dB °C MHz mA mm ms mW ns % pF ps V W decibel degree Celsius Mega Hertz milli Amperes milli meter milli seconds milli Watts nano seconds ohms percent pico Farad pico seconds Volts Watts
digital versatile/video disc electromagnetic interference input/output local area network liquid crystal display phase locked loop small-outline integrated circuit spread spectrum clock spread spectrum clock generator video compact disc wide area network
Unit of Measure
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CY25819
Document History Page
Document Title: CY25819, Spread Spectrum Clock Generator Document Number: 38-07362 Rev.
** *A *B *C *D
ECN No.
112462 122701 448097 2901658 3253540
Issue Date
03/21/02 12/28/02 See ECN 03/30/10 05/10/2011
Orig. of Change
OXC RBI RGL BASH CXQ New Data Sheet
Description of Change
Added power up requirements to maximum rating information. Add Lead-free devices Removed inactive parts from the ordering information table. Updated package diagram and contents. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated in new template.
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07362 Rev. *D
Revised May 10, 2011
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All products and company names mentioned in this document may be the trademarks of their respective holders.
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