CY25823ZXC

CY25823 CK-SSCD Spread Spectrum Differential Clock Specification Features • 3.3V operation • 96- and 100-MHz frequency support • Selectable slew rate control • 200-ps jitter • I2C programmability • 250-µA power-down current • Lexmark Spread Spectrum for best electromagnetic interference (EMI) reduction • 16-pin TSSOP package Block Diagram VDD VDDA REFOUT CLKOUT (SSCG Output) CLKOUT# Clock Input Freq. Divider M Phase Detector Charge Pump Σ Modulating Waveform VCO Post Dividers SDATA SCLK PWRDWN Logic Control Feedback Divider N PLL VSS VSSA Pin Configuration CLKIN S3 S2 S1 PW RDW N REFOUT/SEL SCLK SDATA 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 16 pin TSSOP VDDA VSSA IREF VSSIREF CLKOUT CLKOUT# VSS VDD Cypress Semiconductor Corporation Document #: 38-07579 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised September 02, 2004 CY25823 Pin Definitions Pin No. 1 2,3,4 5 6 S[3:1] PWRDWN REFOUT/SEL Name CLKIN Type Input Input Input I/O Description 3.3V 14.131818-MHz single-ended clock input Spread Spectrum configuration 3.3V LVTTL input for power-down active high, no pull-up or pull-down Latched input during power-up, 1 (10K external pull-up) = 100 MHz or 0 (10K external pull-down) = 96 MHz. After power-up it becomes 14.31818-MHz REFOUT clock. SMBus-compatible SCLK SMBus-compatible SDATA 3.3V power supply for logic and outputs Ground for logic and outputs 0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output 0.7V 96-MHz or 100-MHz Spread Spectrum differential clock output Current reference ground Typically a precision 475Ω external resistor is connected between this pin and VSSIREF to set IOUT (drive current) of CLKOUT differential driver. Ground for PLL 3.3V power supply for PLL 7 8 9 10 11 12 13 14 SCLK SDATA VDD VSS CLKOUT# CLKOUT VSSIREF IREF Input I/O 3.3V Ground Output Output Ground Input 15 16 VSSA VDDA Ground 3.3V Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions such as individual clock output buffers can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operation from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individual indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol.The combined 7 bits slave address and read/write bit form a complete block write (D4h) or block read (D5h) command. Table 1. Command Code Definition Bit 7 (6:0) 0 = Block read or block write operation 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Description Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 Start Slave address – 7 bits (D4) Write = 0 Acknowledge from slave Description Bit 1 2:8 9 10 Start Slave address – 7 bits (D5) Read = 0 Acknowledge from slave Block Read Protocol Description Document #: 38-07579 Rev. *C Page 2 of 12 CY25823 Table 2. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Description Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Byte Count – 8 bits Acknowledge from slave Data byte 0 – 8 bits Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave ...................... Data Byte (N–1) –8 bits Acknowledge from slave Data Byte N –8 bits Acknowledge from slave Stop Bit 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits (D4) Write = 1 Acknowledge from slave Command Code – 8 bits '100000xx' stands for byte operation, bits[1:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Data byte from master – 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 Start Slave address – 7 bits (D5) Read = 1 Acknowledge from slave Command Code – 8 bits '100000xx' stands for byte operation, bits[1:0] of the command code represents the offset of the byte to be accessed Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Data byte from slave – 8 bits Not Acknowledge Stop Byte Read Protocol Description Block Read Protocol Description Command Code – 8 bits '00000000' stands for block operation Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte count from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data byte from slave – 8 bits Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not Acknowledge Stop 19 20:27 28 29 19 20 21:27 28 29 30:37 38 39 Byte 0: Control Register Bit 7 6 5 4 3 0 S1 S2 S3 SEL100/96# @Power-up Pin# 11, 12 11, 12 11, 12 11, 12 6 SS0 SS1 SS2 SS3 SEL100/96# Name – – – – Select output frequency, 1 = 100 MHz, 0 = 96 MHz Pin Description Document #: 38-07579 Rev. *C Page 3 of 12 CY25823 Byte 0: Control Register (continued) Bit 2 1 0 0 1 0 11, 12 Spread Enable HW/SW Control @Power-up Pin# Name Pin Description Reserved must equal 0 Spread spectrum enable, 0 = Disable, 1 = Enable Hardware/software control of S[3:0], and output frequency. 0 = hardware control, 1= software control. Table 4. Spread Spectrum Select (Charge Pump = 00 or Default Condition) SS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Down Down Down Down Center Center Center Center Center Center Center Center Spread Amount % 0.65 0.80 0.90 1.10 1.30 1.40 1.80 2.25 ±0.25 ±0.30 ±0.40 ±0.45 ±0.60 ±0.80 ±1.00 ±1.10 Table 5. Spread Spectrum Select (Charge Pump = 11 and 01) SS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Spread Mode Down Down Down Down Down Down Down Down Center Center Center Center Center Center Center Center Spread Amount % (Charge pump = 11) 0.80 0.90 1.20 1.40 1.60 1.75 2.20 2.60 ±0.38 ±0.40 ±0.50 ±0.60 ±0.75 ±1.00 ±1.15 ±1.30 Spread Amount % (Charge pump = 01) 0.90 1.10 1.40 1.60 2.00 2.20 2.75 3.30 ±0.40 ±0.50 ±0.60 ±0.70 ±0.90 ±1.25 ±1.45 ±1.65 Document #: 38-07579 Rev. *C Page 4 of 12 CY25823 Byte1[7:2] Control Register Bit 7 6 5 4 3 2 0 0 0 0 0 1 11,12 CLKEN @Pup Pin# Name Pin Description Reserved set equal to ‘0’ Reserved set equal to ‘0’ Reserved set equal to ‘0’ Reserved set equal to ‘0’ Reserved set equal to ‘0’ CLKOUT/CLKOUT# enable 0 =Disable, 1 = Enable Byte 1: [1:0] Control Register (Charge Pump Settings) Bit 1 0 0 0 @Pup Default Value 0 0 One Step Higher Than Default 1 1 Two Steps Higher Than Default 1 0 Bytes 2 through 5: Reserved Registers Byte 6: Vendor/Revision ID Register Bit 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 @Pup Pin# – – – – – – – – Name – – – – – – – – Revision ID Bit 3 Revision ID Bit 2 Revision ID Bit 1 Revision ID Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 spread percentage than the default value(00). The ‘01’ option is the highest spread option for maximum EMI reduction. Pin Description Spread Enable and Spread Select[3:0] Spread Enable and Spread Select[3:0] register bits are used to enable and disable spread spectrum on CLKOUT and to change the spread modulation. When the spread selection changes, the CLKOUT output transits to the target spread selection without deviating from clock specifications. At device power-up spread spectrum is enabled and hardware control mode is enabled. The initial spread-spectrum configuration is determined by the S[3:1] pins, which correspond to the S[3:1] bits in Table 4. The S0 configuration bit is hard-coded to zero when hardware control mode is selected. All four spread spectrum configuration bits, S[3:0], can also be set when the device is in the software control mode. PWRDWN (Power-down) Clarification The PWRDWN (Power-down) pin is used to shut off the clock prior to shutting off power to the device. PWRDWN is an asynchronous active HIGH input. This signal is synchronized internally to the device powering down the clock synthesizer. PWRDWN also is an asynchronous function for powering up the system. When PWRDWN is high, all clocks are tri-stated and the oscillator and PLL are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the stopped state. The CLKIN input must be on and within specified operating parameters before PWRDWN is asserted and it must remain in this state while PWRDWN is asserted, see Figure 1. When PWRDWN is de-asserted (CLKIN starts after powerdown de-assertion to meet the IDD≤250µA specification) the clocks should remain stopped until the VCO is stable and within specification (tSTABLE)., see Figure 2. Charge Pump Select Byte1 [1:0] Programming these bits (Byte1[1:0]) via I2C enables the user to have more spread percentage options as described in Table 5. At the start up the default value for byte1[1:0] bits is set to ‘00’, this value can be changed via I2C to have higher spread percentage on CLKOUT and CLKOUT#. Setting the byte[1:0] bits to ‘11’ allows the user to have a slightly higher Document #: 38-07579 Rev. *C Page 5 of 12 CY25823 PW RDW N C L K IN C lo c k V C O C LKO UT CLKO UT# REFOUT Figure 1. Power-down Assertion On O ff TpHZ VDD PWRDWN CLKIN Clock VCO CLKOUT CLKOUT# REFOUT Figure 2. Power-down Deassertion TpZH Off Starting Tstable Stable IR E F M IR E F + 3.3V C1 IO U T - 2R V REF ∼ 1 .1V R C LK OUT C LK OUT # R REF Figure 3. Current Reference Circuit Document #: 38-07579 Rev. *C Page 6 of 12 CY25823 CLKOUT/CLKOUT# Enable Clarification The CLKOUT enable I2C register bit (Byte1, bit2) is used to enable/disable the CLKOUT clock. The PLL and crystal oscillator remains on when the outputs are disabled. When CLKOUT is disabled, the disabled clock is three-stated. The transition to this mode (three-state) is glitch free. Similarly, when CLKOUT is enabled the clock starts in a predictable manner without any glitches or abnormal behavior. Current Reference, IREF The details of the current reference circuit are shown in Figure 3. The operational amplifier in the current reference circuit drives the gate of MIREF with feedback to establish VREF = 1.1V at both inputs of the amplifier. Thus the reference current is established according to the following formula: IREF = 1.1V / RREF where RREF is the external resistor and 1.1V is the reference voltage. The IREF is scaled by 6x at the output stage and IOUT is given as: IOUT = 6 x IREF. The recommended value for RREF is 475 Ohms, which corresponds to the IREF of 2.32mA. Document #: 38-07579 Rev. *C Page 7 of 12 CY25823 Absolute Maximum Conditions Parameter VDD VDDA VIN TS TA TJ ØJC ØJA ESDHBM Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Relative to VSS Non-functional Functional Functional Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) MIL-STD-883, Method 3015 Condition Min. –0.5 –0.5 –0.5 –65 0 – – – 2000 Max. 4.6 4.6 VDD + 0.5 150 70 150 33.89 117.36 – Unit V V VDC °C °C °C °C/W °C/W V DC Electrical Specifications Parameter VDD VDDA VILI2C VIHI2C VIL VIH IIL IOZ IDD IDDS CIN COUT LIN RPU RREF Description Power supply for logic and outputs Power supply for PLL Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current High-impedance Output Current Dynamic Supply Current without output load Total Power Supply Current in Shutdown Shutdown active mode (No Input Clock) Input Pin Capacitance Output Pin Capacitance Input Pin Inductance SCLK and SDATA pull-up resistors IREF external reference resistor when PWRDWN = 1 1% tolerance except internal pull-ups resistors, 0 < VIN < VDD Condition 3.3 ± 5% 3.3 ± 5% SDATA, SCLK SDATA, SCLK Min. 3.135 3.135 VSS–0.5 2.0 VSS – 0.5 2.0 –5 –10 – – 2 3 – 50 200 Max. 3.465 3.465 0.8 VDD 0.8 VDD 5 10 50 250 5 6 5 200 500 Unit V V V V V V µA µA mA µA pF pF nH kΩ W AC Electrical Specifications Parameter TDC TR / TF TCCJ LACC TDC TPERIOD TPERIOD TCCJ Duty Cycle Rise and Fall Times Description Condition Measured at 1.5V crossing point Measured between 0.8V and 2.0V (REFOUT with max. 30 pF Lumped capacitive load) As an average over 1-µs duration Over 150 ms Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Measured at crossing point VOX Min. 40 – Max. 60 1.2 Unit % ns CLKIN/REFOUT AC Specifications Cycle to Cycle Jitter Long-term Accuracy CLKOUT and CLKOUT# Duty Cycle 100 MHz CLKOUT and CLKOUT# Period 96 MHz CLKOUT and CLKOUT# Period CLKOUT/CLKOUT# Cycle to Cycle Jitter with Spread Spectrum Enabled – – 45 9.990 10.406 – 1000 300 55 10.010 10.427 200 ps ppm % ns ns ps CLKOUT/CLKOUT# AC Specifications Document #: 38-07579 Rev. *C Page 8 of 12 CY25823 AC Electrical Specifications (continued) Parameter TR / TF TRFM Tstable[1] ∆TR ∆TF VHIGH VLOW VOX VOVS VUDS VRB Description Condition Min. 175 – – – – 660 –150 250 – –0.3 Measure SE – Max. 700 20 3.0 125 125 850 – 550 VHIGH + 0.3 – 0.2 Unit ps % ms ps ps mv mv mv V V V CLKOUT and CLKOUT# Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V Rise/Fall Matching All clock stabilization from Power-up Rise Time Variation Fall Time Variation Voltage High Voltage Low Crossing Point Voltage at 0.7V Swing Maximum Overshoot Voltage Minimum Undershoot Voltage Ring Back Voltage Determined as a fraction of 2*(TR – TF)/(TR + TF) Application Schematic[2,3] V DD 1 V DDA CLKIN V DD 16 9 0.1 µF C1 5% 33Ω 33Ω 5% 14 R3 475Ω 1% R7 49.9Ω 1% R6 49.9Ω 1% 2 3 4 S3 S2 S1 CLKOUT CLKOUT# 12 11 R5 R4 Source Termination 7 8 5 V DD 6 10ΚΩ R1 5% SCLOCK SDA TA PW RDW N IREF V SSIREF V SS V SSA 13 10 15 Separate Ground REFOUT/SEL 33Ω R2 5% Figure 4. Application Schematic Notes: 1. Not 100% tested, guaranteed by design. 2. VDD and VDDA should be tied together and connected to 3.3V. 3. VSSIREF and VSS are tied together and are common ground. Document #: 38-07579 Rev. *C Page 9 of 12 CY25823 TRise (CLCKOUT) VOH = 0.525V CL KO UT # T OU LK C VCROSS VOL = 0.175V TFall (CLCKOUT) Figure 5. Single-ended Measurement Points for TRise and TFall (CLKOUT and CLKOUT#) CLKO UT 33Ω 4 9 .9 Ω 33Ω TPCB M e a s u re m e n t P o in t 2pF C LKO U T# IR E F TPCB 4 9 .9 Ω M e a s u re m e n t P o in t 2pF 475Ω Figure 6. 0.7V Load Configuration Ordering Information Part Number CY25823ZXC CY25823ZXCT Package Type 16-pin TSSOP (Lead-free) 16-pin TSSOP – Tape and Reel (Lead-free) Product Flow Commercial, 0°C to 70°C Commercial, 0°C to 70°C Document #: 38-07579 Rev. *C Page 10 of 12 CY25823 Package Drawing and Dimension 16-lead TSSOP 4.40 MM Body Z16.173 PIN 1 ID 1 DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177] PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG. 16 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 4.90[0.193] 5.10[0.200] 51-85091-*A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07579 Rev. *C Page 11 of 12 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY25823 Document History Page Document Title: CY25823 CK-SSCD Spread Spectrum Differential Clock Specification Document #: 38-07579 Rev. *C Rev. ** *A *B *C ECN No. 131662 203801 252269 260155 Issue Date 12/10/03 See ECN See ECN See ECN Orig. of Change RGL RGL RGL RGL New Data Sheet Fixed the I2C Block Read/Write Protocol and Byte Read/Write Protocol tables Corrected to New Lead Free Code Minor Change: Corrected the package diagram Description of Change Document #: 38-07579 Rev. *C Page 12 of 12