CY26126SC

5 Advance Information CY26126 Dual Output 125-MHz Clock Generator Features • Integrated phase-locked loop • Low skew, low jitter, high accuracy outputs • 3.3V Operation Part Number CY26126 Outputs 2 Input Frequency Range 25 MHz Output Frequencies 2 copies of 125 MHz (3.3V) Benefits Highest-performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Logic Block Diagram 25 XIN XOUT P Comp OSC. Q VCO P OUTPUT MULTIPLEXER AND DIVIDERS 125 MHz 125 MHz PLL OE VDD VSS Pin Configurations CY26126 8-pin SOIC XIN VDD OE VSS 1 2 3 4 8 7 6 5 XOUT CLKB CLKA VSS Cypress Semiconductor Corporation Document #: 38-07351 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 Advance Information Pin Summary Name XIN VDD OE VSS VSS CLKA CLKB XOUT [1] CY26126 Pin Number 1 2 3 4 5 6 7 8 Description Reference Input 3.3V Voltage Supply Output Enable Ground Ground 125-MHz Clock Output A 125-MHz Clock Output B Reference Output Absolute Maximum Conditions Parameter VDD TS TJ Storage Description Supply Voltage Temperature[2] Junction Temperature Digital Inputs Digital Outputs referred to VDD Electro-Static Discharge VSS – 0.3 VSS – 0.3 2 Min. –0.5 –65 Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 Unit. V °C °C V V kV Recommended Operating Conditions Parameter VDD TA CLOAD Pmax fREF tPU Description Operating Voltage Ambient Temperature Max. Load Capacitance Max. Output Power Dissipation Reference Frequency Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 25 500 Min. 3.14 0 Typ. 3.3 Max. 3.47 70 15 150 Unit V °C pF mW MHz ms DC Electrical Characteristics Parameter IOH IOL VIH VIL CIN IIZ Description Output High Current Output Low Current Input High Voltage Input Low Voltage Input Capacitance Input Leakage Current Current 5 35 Conditions VOH = VDD – 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V CMOS Levels 70% of VDD CMOS Levels 30% of VDD Min. 12 12 0.7 0.3 7 Typ. 24 24 Max. Unit mA mA VDD VDD pF µA mA Supply Current Sum of Core and Output IDD Notes: 1. Float XOUT pin if XIN is driven by reference clock (as opposed to crystal). 2. Rated for 10 years. Document #: 38-07351 Rev. *A Page 2 of 5 Advance Information AC Electrical Characteristics (VDD = 3.3V)[3] Parameter t3 t4 t9 t10 Description Output Duty Cycle Falling Edge Slew Rate Clock Jitter PLL Lock Time Conditions Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Fall Time, 80% - 20% of VDD Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 CY26126 Max. 55 Unit % V/ns V/ns Rising Edge Slew Rate Output Clock Rise Time, 20% - 80% of VDD 200 3 ps ms Note: 3. Not 100% tested. Test Circuit VDD 0.1 µF OUTPUTS CLK out CLOAD VDD 0.1 µF GND t1 t2 CLK 50% Figure 1. Duty Cycle Definition; DC = t2/t1 t3 80% t4 CLK 20% Figure 2. Rise and Fall Time Definitions Ordering Information Ordering Code CY26126SC Package Name S8 Package Type 8-Pin SOIC Operating Range Commercial Operating Voltage 3.3V Document #: 38-07351 Rev. *A Page 3 of 5 Advance Information Package Diagram 8-Lead (150-Mil) SOIC S8 CY26126 51-85066-A Document #: 38-07351 Rev. *A Page 4 of 5 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Advance Information CY26126 Document Title: CY26126 Dual Output 125-MHz Clock Generator Document Number: 38-07351 REV. ** *A ECN NO. 112233 121891 Issue Date 03/01/02 12/14/02 Orig. of Change CKN RBI New data sheet Power up requirements added to Operating Conditions Information Description of Change Document #: 38-07351 Rev. *A Page 5 of 5