CY26187SC-2

CY26187SC-2

  • 厂商:

    CYPRESS(赛普拉斯)

  • 封装:

  • 描述:

    CY26187SC-2 - Broadcom Reference Design Clock Generator - Cypress Semiconductor

  • 详情介绍
  • 数据手册
  • 价格&库存
CY26187SC-2 数据手册
THIS SPEC IS OBSOLETE Spec No: 38-07131 Spec Title: CY26187-2 Broadcom Reference Design Clock Generator Sunset Owner: RGL Replaced by: NA 1CY2295 CY26187-2 Broadcom Reference Design Clock Generator Features • Integrated phase-locked loop • Low skew, low jitter, high accuracy outputs • 3.3V Operation Part Number CY26187-2 Outputs 1 Broadcom Reference Design BCM5680_5404 Input Frequency 50 MHz Output Frequencies 1 copy of 142.8 MHz (3.3V) Benefits Highest Performance PLL tailored for multimedia applications Meets critical timing requirements in complex system designs Logic Block Diagram OUTPUT MULTIPLEXER AND DIVIDERS VCO P 50 XIN XOUT P Comp OSC Q 142.8 MHz PLL OE VDD VDD VSS VSS Pin Configuration CY26187 8-pin SOIC XIN AVDD OE AVSS 1 2 3 4 8 7 6 5 XOUT VSS 142.8 MHz VDD Cypress Semiconductor Corporation Document #: 38-07131 Rev. OBS • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 02, 2004 CY26187-2 Summary Name XIN[1] AVDD OE AVSS VDD 142.8 MHz VSS XOUT[1] Pin Number 1 2 3 4 5 6 7 8 Description Reference Crystal Input Analog Voltage Supply Output enable (0-off; 1-on) Ground Voltage Supply 142.8-MHz clock output Ground Reference Crystal Output Absolute Maximum Conditions Parameter VDD TS TJ Storage Description Supply Voltage Temperature[2] –65 VSS – 0.3 VSS – 0.3 2 Junction Temperature Digital Inputs Digital Outputs referred to VDD Electro-Static Discharge Min. Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 Unit V °C °C V V kV Recommended Operating Conditions Parameter VDD TA CLOAD Pmax fREF tPU Description Operating Voltage Ambient Temperature Max. Load Capacitance Max. Output Power Dissipation, 8-pin package Reference Frequency Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) 0.05 50 500 Min. 3.135 0 Typ. 3.3 Max. 3.465 70 15 150 Unit V C pF mW MHz ms DC Electrical Characteristics Parameter Name Output High Current Output Low Current Input Capacitance Input Leakage Current IVDD 3.3V, All outputs @ 10 MHz Notes: 1. Float XOUT pin if XIN is driven by reference clock (as opposed to crystal). 2. Rated for 10 years. Description VOH = VDD – 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 12 12 Typ. 24 24 Max. Unit mA mA 7 5 35 pF µA mA Document #: 38-07131 Rev. OBS Page 2 of 5 CY26187-2 AC Electrical Characteristics (VDD = 3.3V) (3.) Parameter t3 t4 t9 t10 Name Output Duty Cycle Description Duty Cycle is defined in Figure 1, 50% of VDD Min. 45 0.8 0.8 Typ. 50 1.4 1.4 200 3 Max. 55 Unit % V/ns V/ns ps ms Rising Edge Slew Rate Output Clock Rise Time, 20%-80% of VDD Falling Edge Slew Rate Output Clock Fall Time, 80% to 20% of VDD Clock Jitter PLL Lock Time Peak to Peak period jitter Note: 3. Not 100% tested. Test Circuit VDD 0.1 µF OUTPUTS CLK out CLOAD VDD 0.1 µF GND t1 t2 CLK 50% Figure 1. Duty Cycle Definition; DC = t2/t1. t3 80% t4 CLK 20% Figure 2. Rise and Fall Time Definitions. Ordering Information Ordering Code CY26187SC-2 Package Name S8 Package Type 8-Pin SOIC Operating Range Commercial Operating Voltage 3.3V Document #: 38-07131 Rev. OBS Page 3 of 5 CY26187-2 Package Diagram 8-Lead (150-Mil) SOIC S8 51-85066-A Document #: 38-07131 Rev. OBS Page 4 of 5 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY26187-2 Revision History Document Title: CY26187-2 Broadcom Reference Design Clock Generator Document Number: 38-07131 REV. ** *A OBS ECN NO. 110096 121872 294822 Issue Date 02/19/02 12/14/02 See ECN Orig. of Change CKN RBI RGL Description of Change New data sheet Power up requirements added to Operating Conditions Information TO Obsolete the DS Document #: 38-07131 Rev. OBS Page 5 of 5
CY26187SC-2
物料型号: - 型号:CY26187-2

器件简介: - CY26187-2是一款集成相位锁定环(PLL)的时钟发生器,专为多媒体应用设计,具有低偏斜、低抖动和高准确度输出,支持3.3V操作。

引脚分配: - XIN1:1号引脚,参考晶振输入 - AVDD:2号引脚,模拟电压供电 - OE:3号引脚,输出使能(0-关闭;1-开启) - AVSS:4号引脚,地 - VDD:5号引脚,电压供电 - 142.8 MHz:6号引脚,142.8-MHz时钟输出 - VSS:7号引脚,地 - XOUT[1]:8号引脚,参考晶振输出

参数特性: - 供电电压(VDD):3.135V至3.465V - 环境温度(TA):0至70摄氏度 - 最大负载电容(CLOAD):15pF - 最大输出功率耗散(P max):150mW - 参考频率(fREF):50MHz - 电源上电时间(tpu):0.05至500ms

功能详解: - 该器件包含一个高性能PLL,适用于复杂系统设计中的关键时序要求,提供1个输出,为Broadcom参考设计BCM5680 5404,输入频率为50MHz,输出频率为142.8MHz(3.3V)。

应用信息: - 主要应用于需要精确时钟源的多媒体应用领域。

封装信息: - 8引脚SOIC封装。
CY26187SC-2 价格&库存

很抱歉,暂时无法提供与“CY26187SC-2”相匹配的价格&库存,您可以联系我们找货

免费人工找货