CY26200SI

CY26200 T1/E1 Clock Generator Features • Integrated phase-locked loop (PLL) • Low-jitter, high-accuracy outputs • 3.3V operation Part Number CY26200 Outputs 1 Input Frequency Range 19.44 MHz Benefits • High-performance PLL tailored for T1/E1 clock generation • Meets critical timing requirements in complex system designs • Enables application compatibility Output Frequencies 1.544 MHz/2.048 MHz (selectable) Logic Block Diagram 19.44 XIN XOUT OSC Q Φ VCO P PLL OUTPUT DIVIDERS CLK1 AVDD AVSS VDD VSS Pin Configuration CY26200 8-pin SOIC XIN AVDD FS AVSS 1 2 3 4 8 7 6 5 XOUT VSS CLK1 VDD Table 1. CY26200 Frequency Select Option Frequency Select 0 1 CLK1 1.544 2.048 Unit MHz MHz Cypress Semiconductor Corporation Document #: 38-07335 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 3, 2005 CY26200 Pin Summary Pin Name XIN AVDD FS AVSS VDD CLK1 VSS XOUT[1] Pin Number 1 2 3 4 5 6 7 8 19.44-MHz Reference Input Analog Voltage Supply Frequency Select – see Table 1 Analog Ground Voltage Supply 1.544-MHz/2.048-MHz Clock Output Ground Reference Output Pin Description Absolute Maximum Conditions Parameter VDD TS TJ Storage Description Supply Voltage Temperature[2] Junction Temperature Digital Inputs Digital Outputs Referred to VDD Electrostatic Discharge VSS – 0.3 VSS – 0.3 2000 Min. –0.5 –65 Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 Unit V °C °C V V V Recommended Operating Conditions Parameter VDD/AVDD TA TA CLOAD fREF tPU Description Operating Voltage Ambient Temperature (Commercial) Ambient Temperature (Industrial) Max. Load Capacitance Reference Frequency Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.05 19.44 500 Min. 3.135 0 –40 Typ. 3.3 Max. 3.465 70 +85 15 Unit V °C °C pF MHz ms DC Electrical Characteristics (Commercial) Parameter IOH IOL CIN IIZ IDD Description Output High Current Output Low Current Input Capacitance Input Leakage Current Supply Current Sum of Core and Output Current 5 20 Conditions VOH = VDD – 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 12 12 Typ. 24 24 7 Max. Unit mA mA pF µA mA DC Electrical Characteristics (Industrial) Parameter IOH IOL CIN IIZ IDD Description Output High Current Output Low Current Input Capacitance Input Leakage Current Supply Current Sum of Core and Output Current 5 25 Conditions VOH = VDD – 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 11 11 Typ. 24 24 7 Max. Unit mA mA pF µA mA Notes: 1. Float XOUT if XIN is externally driven 2. Rated for 10 years Document #: 38-07335 Rev. *B Page 2 of 5 CY26200 AC Electrical Characteristics (VDD = 3.3V, Commercial) Parameter[3] DC t3 t4 t9 t10 Description Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate Clock Jitter PLL Lock Time Conditions Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20% - 80% of VDD Output Clock Fall Time, 80% - 20% of VDD Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 200 3 Max. 55 Unit % V/ns V/ns ps ms AC Electrical Characteristics (VDD = 3.3V, Industrial) Parameter[3] DC t3 t4 t9 t10 Name Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20% - 80% of VDD Output Clock Fall Time, 80% - 20% of VDD Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 200 3 Max. 55 Unit % V/ns V/ns ps ms Test Circuit V DD 0.1 mF OUTPUTS CLK out C LOAD GND t3 t1 t2 CLK 50% 50% 80% CLK 20% t4 Figure 2. Rise and Fall Time Definitions Figure 1. Duty Cycle Definition; DC = t2/t1 Ordering Information Ordering Code CY26200SC CY26200SCT CY26200SI CY26200SIT Lead-free CY26200SXC CY26200SXCT CY26200SXI CY26200SXIT Notes: 3. Not 100% tested Package Type 8-lead SOIC 8-lead SOIC - Tape and Reel 8-lead SOIC 8-lead SOIC - Tape and Reel 8-lead SOIC 8-lead SOIC - Tape and Reel 8-lead SOIC 8-lead SOIC - Tape and Reel Operating Range Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Operating Voltage 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V Document #: 38-07335 Rev. *B Page 3 of 5 CY26200 Package Diagram 8-lead (150-Mil) SOIC S8 8 Lead (150 Mil) SOIC - S08 PIN 1 ID 4 1 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 2. PIN 1 ID IS OPTIONAL, ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 3. REFERENCE JEDEC MS-012 0.230[5.842] 0.244[6.197] 0.150[3.810] 0.157[3.987] 4. PACKAGE WEIGHT 0.07gms PART # S08.15 STANDARD PKG. 5 8 SZ08.15 LEAD FREE PKG. 0.189[4.800] 0.196[4.978] SEATING PLANE 0.010[0.254] 0.016[0.406] X 45° 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 51-85066-*C All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07335 Rev. *B Page 4 of 5 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY26200 Document History Page Document Title: CY26200 T1/E1 Clock Generator Document Number: 38-07335 REV. ** *A *B ECN No. 111745 121890 400148 Issue Date 05/06/02 12/14/02 See ECN Orig. of Change CKN RBI RGL Description of Change New Data Sheet Power up requirements added to Operating Conditions Information Added lead-free devices Document #: 38-07335 Rev. *B Page 5 of 5