CY26580OI-2

CY26580 PacketClock™ Network Applications Clock Features Benefits ■ Integrated phase-locked loop (PLL) ■ Internal PLL with precision operation ■ Low-jitter, high-accuracy outputs ■ Meets critical timing requirements in complex system designs ■ 3.3V operation ■ Enables application compatibility Table 1. Frequency Table Part Number Outputs Input Frequency Output Frequencies CY26580-1 2 125MHz or 25-MHz driven 100 MHz, 133.33 MHz Logic Block Diagram CLK Φ Q OSC. VCO OUTPUT MULTIPLEXER AND DIVIDERS P 133.33 MHz 100 MHz PLL SEL_25 SEL_CLK VDD VDD GND GND Table 2. Input Select Options SEL_25 SEL_CLK X 0 Input Type 0 1 Driven 125 1 1 Driven 25 Cypress Semiconductor Corporation Document #: 38-07536 Rev. *C Input Frequency CLK1 CLK2 Unit 133.33 100 MHz 133.33 100 MHz Do not use • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 22, 2008 [+] Feedback CY26580 Pin Configuration Figure 1. CY26580 20-pin SSOP (QSOP) NC 1 20 NC NC 2 19 SEL_CLK NC 100 MHz CLK 3 18 VDD 4 17 NC GND 5 16 VDD 6 15 NC NC 7 NC 8 14 13 GND NC NC 9 10 12 NC 11 SEL_25 133 MHz Table 3. Pin Definition Pin Name Pin Number Pin Description NC 1 No Connect NC 2 No Connect CLK 3 Reference Input VDD 4 Voltage Supply NC 5 No Connect GND 6 Ground NC 7 No Connect NC 8 No Connect NC 9 No Connect 133 MHz 10 133.33-MHz Clock Output SEL_25 11 Reference Frequency Select Input; 0 = 125 MHz, 1 = 25 MHz, weak internal pull up NC 12 No Connect NC 13 No Connect GND 14 Ground NC 15 No Connect VDD 16 Voltage Supply 100 MHz 17 100-MHz Clock Output NC 18 No Connect SEL_CLK 19 Reference Select Input; Set to 1 = Driven, weak internal pull up NC 20 No Connect Document #: 38-07536 Rev. *C Page 2 of 6 [+] Feedback CY26580 Absolute Maximum Conditions[1] Junction Temperature ................................ –40°C to +125°C Data Retention at Tj = 125°C ................................> 10 years Supply Voltage (VDD)........................................ –0.5 to +7.0V Package Power Dissipation...................................... 350 mW DC Input Voltage ....................................... –0.5V to VDD+0.5 ESD (Human Body Model) MIL-STD-883.................... 2000V Storage Temperature (Non-condensing) .... –55°C to +125°C Recommended Operating Conditions Parameter Description Min Typ. Max Unit V VDD Supply Voltage 3.14 3.3 3.47 TA, I-grade Ambient Temperature, Industrial –40 – 85 °C CLOAD Max. Load Capacitance – – 15 pF fREF Reference Frequency – 125, 25 – MHz Min Typ. Max Unit DC Electrical Specifications Parameter[2] Description Conditions IOH Output High Current VOH = VDD – 0.5, VDD = 3.3V 12 24 – mA IOL Output Low Current VOL = 0.5, VDD = 3.3V 12 24 – mA IIH Input High Current VIH = VDD – 5 10 μA IIL Input Low Current VIL = 0V – – 50 μA VIH Input High Voltage CMOS levels, 70% of VDD 0.7 – – VDD VIL Input Low Voltage CMOS levels, 30% of VDD – – 0.3 VDD IDD Supply Current VDD Current, no load – 35 50 mA RUP Pull up resistor on Inputs VDD = 3.14 to 3.47V, measured VIN = 0V – 100 150 kΩ Min Typ. Max Unit 0 ppm AC Electrical Specifications Parameter[2] Description Conditions Ferror Frequency Error All clocks DC Output Duty Cycle Duty Cycle is defined in Figure 3, 50% of VDD 45 50 55 % ER Rising Edge Rate Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 4. 0.8 1.4 2 V/ns EF Falling Edge Rate Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 4. 0.8 1.4 2 V/ns t9 Clock Jitter CLK1, CLK2 Peak-Peak period jitter – 100 – ps t10 PLL Lock Time – – 3 ms Figure 2. Test and Measurement Setup VDDs 0.1 μF DUT Outputs CLOAD GND Notes 1. Above which the useful life may be impaired. For user guidelines, not tested. 2. Guaranteed by characterization, not 100% tested. Document #: 38-07536 Rev. *C Page 3 of 6 [+] Feedback CY26580 Voltage and Timing Definitions Figure 3. Duty Cycle Definition t1 t2 VDD 50% of VDD Clock Output 0V Figure 4. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4 t3 t4 V DD 80% of V DD Clock Output 20% of VDD 0V Ordering Information Ordering Code[3] Package Type Temperature Range Operating Voltage CY26580OI–2[4] 20-pin SSOP (QSOP) Industrial 3.3V CY26580OI–2T[4] 20-pin SSOP (QSOP) – Tape and Reel Industrial 3.3V CY26580KOI–2 20-pin SSOP (QSOP) Industrial 3.3V CY26580KOI–2T 20-pin SSOP (QSOP) – Tape and Reel Industrial 3.3V CY26580KQXI–2 20-pin SSOP (QSOP) Industrial 3.3V CY26580KQXI–2T 20-pin SSOP (QSOP) – Tape and Reel Industrial 3.3V Pb-Free Notes 3. Part numbers ending in -1 and -1T have been replaced by part numbers ending in -2 and -2T. Specifications for -1, -1T, -2 and -2T part numbers are identical. 4. Not recommended for new designs. Document #: 38-07536 Rev. *C Page 4 of 6 [+] Feedback CY26580 Package Drawing and Dimensions Figure 5. 20-lead QSOP O201 and SQ201 51-85054-*B Document #: 38-07536 Rev. *C Page 5 of 6 [+] Feedback CY26580 Document History Page Document Title: CY26580 PacketClock™ Network Applications Clock Document #: 38-07536 Rev. *C REV. ECN NO. Submission Date Orig. of Change ** 127357 06/17/03 RGL *A 128564 09/12/03 IJA Change pin 1 to NC and pin 3 to CLK *B 216828 See ECN RGL Removed Preliminary *C 2442066 See ECN Description of Change New Data Sheet KVM/AESA Updated template. Added Note “Not recommended for new designs.” Added Note explaining “-1” and “-2” part numbers. Removed part numbers CY26580OI-1 and CY26580OI-1T. Added part number CY26580OI–2T, CY26580KOI–2, CY26580KOI–2T, CY26580KQXI–2, and CY26580KQXI–2T in ordering information table. Updated figure caption for package drawing. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers PSoC Solutions psoc.cypress.com clocks.cypress.com General Low Power/Low Voltage psoc.cypress.com/solutions psoc.cypress.com/low-power Wireless wireless.cypress.com Precision Analog Memories memory.cypress.com LCD Drive psoc.cypress.com/lcd-drive image.cypress.com CAN 2.0b psoc.cypress.com/can USB psoc.cypress.com/usb Image Sensors psoc.cypress.com/precision-analog © Cypress Semiconductor Corporation, 2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07536 Rev. *C Revised May 22, 2008 Page 6 of 6 PacketClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback