CY27022
Clock Generator for Net-MD System
Features
Description
■
Supports Clock Requirement for Mini Disc
■
16.9344 MHz Crystal or Clock Input
The CY27022 is a clock generator that integrates clock requirements for a Net-MD system.
■
12.000 MHz for USB Clock Output
■
10.0352 MHz for Controller Clock Output
■
90.3168 MHz/180.6336 MHz Selectable Clock Output
■
Load Capacitance for Crystal (Cl = 12.1 pF Typ)
■
3.3V Operation
■
8-pin SOIC Package
The CY27022 supports USB clock, Mini Disc, and CPU clock
requirements.
Table 1. Frequency Table (Input = 16.9344 MHz)
Pin Number
Name
Output Frequency
FS
1
CLKC
12.000 MHz
x
5
CLKB
90.3168 MHz
0
5
CLKB
180.6336 MHz
1
6
CLKA
10.0352 MHz
x
Pinout
Figure 1. Pin Diagram - 8-Pin SOIC
CLKC
1
GND
2
XIN
XOUT
8
FS
7
VDD
3
6
CLKA
4
5
CLKB
SOIC
Table 2. Pin Definition - 8 SOIC
Pin
Number Pin Name
I/O
Description
O
12.000 MHz clock output
1
CLKC
2
GND
3
XIN
I
16.9344 MHz reference crystal or external clock input
4
XOUT
O
Reference crystal feedback (float if XIN is driven by external reference clock)
5
CLKB
O
Selectable clock output, see Table 1.
6
CLKA
O
10.0352 MHz clock output
7
VDD
8
FS
PWR Device Ground
PWR +3.3V power supply
I
Frequency selection input pin. This pin controls the frequency presented on CLKB. Internal pull up
Cypress Semiconductor Corporation
Document Number:38-07293 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 10, 2009
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CY27022
Maximum Ratings
Maximum Input Voltage Relative to VDD:.................. VDD + 0.3V
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric fields. However,
precautions are taken to avoid application of any voltage higher
than the maximum rated voltages to this circuit. For proper
operation, Vin and Vout are constrained to the range:
Storage Temperature: ........................................ –65° to +150°C
GND < (Vin or Vout) < VDD
Operating Temperature:.........................................0°C to +70°C
Unused inputs are always to an appropriate logic voltage level
(either GND or VDD).
The voltage on any input or I/O pin cannot exceed the power pin
during power up. These user guidelines are not tested.
Maximum Input Voltage Relative to GND: .........................–0.3V
Maximum ESD Protection ................................................... 2KV
Maximum Power Supply:.....................................................5.5V
Operating Voltage: ..................................................... 2.9V–3.6V
DC Parameters
Table 3. DC Parameters[2] (VDD = 3.3V ±10%, TA = 0 to 70°C)
Parameter
Description
Conditions
Min
VIL
Input low voltage
See Note 1
VIH
Input high voltage
See Note 1
2.0
–72
IIL
Input low current
See Note 1
IIH
Input high current
See Note 1
Idd3.3V
Dynamic supply current
No output load, FS = 1 (180-MHz mode)
VOL
Output low voltage
IOL= 4.0 mA
VOH
Output high voltage
IOH = –4.0 mA
CXTAL
Crystal pin capacitance
XIN, XOUT pin capacitance
Typ
Max
Unit
0.8
V
V
19
-15
μA
10
μA
28
mA
0.4
V
2.4
V
23
pF
AC Parameters
Table 4. AC Parameters[3]
Parameter
Tr1
Tf1
Tr2
Description
Comments
Typ
Max
Unit
Rise time
CLKA and CLKC at rated load[4, 5, 6, 7]
2
3
ns
[4, 5, 6, 7]
2
Fall time
Rise time
Min
3
ns
CLKB at rated load
[4, 5, 6, 7]
1.5
ns
[4, 5, 6, 7]
1.5
ns
3
ms
55
%
250
ps
150
ps
CLKA and CLKC at rated load
Tf2
Fall time
CLKB at rated load
Tpu
Power up to stable output
All output clocks[5]
Tdc
Clock duty cycle
All clocks at rated load[ 6, 7]
Tj1
Tj2
Clock jitter
Clock jitter
45
50
[4, 5, 6, 7]
CLKA and CLKC at rated load
[4, 5, 6, 7]
CLKB at rated load
Notes
1. Applicable to input signal: FS. Internal pull up resistor value may vary between 70k and 170k.
2. The voltage on any input or IO pin cannot exceed the power pin during power up.
3. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with fully loaded outputs
4. Measured between 0.2*VDD and 0.8*VDD Volts.
5. Measured between 0.2*VDD and 0.7*VDD Volts.
6. Clocks trigger at 1.5 Volts.
7. All outputs have a 15 pF load.
Document Number:38-07293 Rev. *E
Page 2 of 4
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CY27022
Ordering Information
Ordering Code
Package Type
Operating Range
Operating Voltage
CY27022SCT
8-pin SOIC - Tape and Reel
Commercial (0 to 70°C)
3.3V±10%
CY27022SXC
8-pin SOIC (Pb-free)
Commercial (0 to 70°C)
3.3V±10%
CY27022SXCT
8-pin SOIC (Pb-free) - Tape and Reel
Commercial (0 to 70°C)
3.3V±10%
Package Drawing and Dimensions
Figure 2. 8-Pin (150-Mil) SOIC
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Document Number:38-07293 Rev. *E
Page 3 of 4
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CY27022
Document History
Document Title: CY27022 Clock Generator for Net-MD System
Document Number: 38-07293
REV.
ECN NO.
Submission
Date
Orig. of
Change
Description of Change
**
116146
08/14/02
OSM
*A
122884
12/22/02
RBI
New Data Sheet
*B
406494
See ECN
XHT/CFT
Obsolete specification. Sunset Review Clean up. Personalized clock chips for
Japanese customer and no longer in use.
*C
1191263
See ECN
KVM
Revived the data sheet as the device is still active. Added Pb-free part
numbers. Updated note 2 to remove mention of multiple supplies and voltage
sequencing. Replaced instances of VSS with GND.
*D
2710266
05/22/09
*E
2748211
08/10/09
Added power up requirements to Maximum Ratings
KVM/PYRS Remove obsolete part number from Ordering Information table: CY27022SC
TSAI
Posting to external web.
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2002-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
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Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number:38-07293 Rev. *E
Revised August 10, 2009
Page 4 of 4
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