CY28339ZXCT

CY28339 Intel CK408 Mobile Clock Synthesizer Features • Compliant with Intel® CK 408 rev 1.1 Mobile Clock Synthesizer specifications • 3.3V power supply • Two differential CPU clocks • Nine copies of PCI clocks • Three copies configurable PCI free-running clocks • Two 48 MHz clocks (USB, DOT) • Five/six copies of 3V66 clocks • • • • One VCH clock One reference clock at 14.318 MHz SMBus support with read-back capabilities Ideal Lexmark profile Spread Spectrum electromagnetic interference (EMI) reduction • Dial-a-Frequency™ features • Dial-a-dB™ features • 48-pin TSSOP package Table 1. Frequency Table[1] S2 S1 CPU (1:2) 3V66 66BUFF(0:2)/ 3V66(0:4) 66IN/3V66–5 PCIF, PCI REF USB/ DOT 1 0 100M 66M 66IN 66-MHz clock input 66IN/2 14.318M 48M 1 1 133M 66M 66IN 66-MHZ clock input 66IN/2 14.318M 48M 0 0 100M 66M 66M 66M 33 M 14.318M 48M 0 1 133M 66M 66M 66M 33 M 14.318M 48M M 0 TCLK/2 TCLK/4 TCLK/4 TCLK/4 TCLK/8 TCLK TCLK/2 Block Diagram X1 X2 XTAL OSC Pin Configuration VDD_REF PWR REF Top View PLL Ref Freq PLL 1 S1:2 VTT_PWRGD## CPU_STOP# 48 VDD_REF XOUT 2 47 REF GND_REF 3 46 S1 VDD_CPU CPUT1:2 PCI7 4 45 PWR Stop Clock Control CPU_STOP# PCI8 5 44 VDD_CPU CPUC1:2 PCIF 6 43 CPUT1 GND_PCI 7 42 CPUC1 VDD_PCI PCIF PCI0 8 41 PWR GND_CPU PCI1 40 VDD_CPU PCI0:2 9 Stop Clock Control PCI2 39 CPUT2 PCI4:8 10 VDD_PCI 11 38 CPUC2 PCI4 37 IREF PCI5 12 13 PCI_STOP# /2 36 S2 PCI6 14 35 USB_48MHz VDD_3V66 GND_3V66 15 34 DOT_48MHz 16 33 66BUFF0/3V66_2 66BUFF1/3V66_3 66BUFF2/3V66_4 17 32 VDD_48 MHz GND_48 MHz 18 31 19 30 VDD_3V66 PWR 3V66_0:1 3V66_2:4/ 66BUFF0:2 PWR 3V66_5/ 66IN PLL 2 SDATA SCLK 3V66_1/VCH 66IN/3V66_5 20 29 PCI_STOP# 3V66_0 USB (48MHz) PD# 21 28 VDD_3V66 DOT (48MHz) VDD_CORE 22 27 GND_CORE VTT_PWRGD# 23 26 GND_3V66 SCLK 24 25 SDATA VDD_48MHz PWR CY28339 1 Divider Network Gate PD# XIN VCH_CLK/ 3V66_1 SMBus Logic Note: 1. TCLK is a test clock driven on the XTAL_IN input during test mode. M = driven to a level between 1.0V and 1.8V. If the S2 pin is at a M level during power-up, a 0 state will be latched into the device’s internal state register. Cypress Semiconductor Corporation Document #: 38-07507 Rev. *A • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised June 25, 2004 [+] Feedback CY28339 Pin Definitions Pin Number Name I/O Description 47 REF0 3.3V 14.318-MHz clock output. 1 XIN 14.318-MHz crystal input. 2 XOUT 14.318-MHz crystal input. 43, 42, 39, 38 CPUT1,CPUC1 CPUT2, CPUC2 Differential CPU clock outputs. 29 3V66_0 3.3V 66-MHz clock output. 31 3V66_1/VCH 3.3V selectable through SMBus to be 66 MHz or 48 MHz. 20 66IN/3V66_5 66-MHz input to buffered 66BUFF and PCI or 66-MHz clock from internal VCO. 17, 18, 19 66BUFF [2:0] /3V66 [4:2] 66-MHz buffered outputs from 66Input or 66-MHz clocks from internal VCO. 6 PCIF 33 MHz clocks divided down from 66Input or divided down from 3V66; PCIF default is free-running. 8, 9, 10, 12, 13, 14, 4, 5 PCI [0:2] PCI [4:6] PCI [7:8] PCI clock outputs divided down from 66Input or divided down from 3V66; PCI [7:8] are configurable as free-running PCI through SMBus.[2] 35 USB_48M Fixed 48-MHz clock output. 34 DOT_48M Fixed 48-MHz clock output. 36 S2 Special 3.3V three-level input for Mode selection. 46 S1 3.3V LVTTL inputs for CPU frequency selection. 37 IREF A precision resistor is attached to this pin which is connected to the internal current reference. 21 PD# 3.3V LVTTL input for Power_Down# (active LOW). 30 PCI_STOP# 3.3V LVTTL input for PCI_STOP# (active LOW). 45 CPU_STOP# 3.3V LVTTL input for CPU_STOP# (active LOW). 24 VTT_PWRGD# 3.3V LVTTL input is a level-sensitive strobe used to determine when S[2:1] inputs are valid and OK to be sampled (Active LOW). Once VTT_PWRGD# is sampled LOW, the status of this input will be ignored. 25 SDATA SMBus-compatible SDATA. 26 SCLK SMBus-compatible SCLK. 11, 15, 28, 40, 44, 48 VDD_PCI, VDD_3V66, VDD_CPU,VDD_RE F 3.3V power supply for outputs. 33 VDD_48 MHz 3.3V power supply for 48 MHz. 22 VDD_CORE 3.3V power supply for phase-locked loop (PLL). 3, 7, 16, 27, 32, 41 GND_REF, GND_PCI, GND_3V66, GND_IREF, GND_CPU Ground for outputs. 23 GND_CORE Ground for PLL. Note: 2. PCI3 is internally disabled and is not accessible. Document #: 38-07507 Rev. *A Page 2 of 18 [+] Feedback CY28339 Two-Wire SMBus Control Interface Serial Control Registers The two-wire control interface implements a Read/Write slave only interface according to SMBus specification. Following the acknowledge of the Address Byte, two additional bytes must be sent: The device will accept data written to the D2 address and data may read back from address D3. It will not respond to any other addresses, and previously set control registers are retained as long as power in maintained on the device. 1. “Command code“ byte 2. “Byte count” byte. Although the data (bits) in the command is considered “don’t care,” it must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowledged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged. Byte 0: CPU Clock Register[3,4] Bit @Pu p Name 7 0 Spread Spectrum Enable. 0 = Spread Off, 1 = Spread On. This is a Read and Write control bit. 6 0 CPU Clock Power-down Mode Select. 0 = Drive CPUT to 2x IREF and drive CPUC LOW 1 = Tri-state all CPU outputs. This is only applicable when PD# is LOW. It is not applicable to CPU_STOP#. 5 0 3V66_1/VC H 4 Description 3V66_1/VCH Frequency Select 0 = 66M selected, 1 = 48M selected. This is a Read and Write control bit. Reserved 3 HW PCI_STOP# Reflects the current value of the internal PCI_STOP# function when read. Internally PCI_STOP# is a logical AND function of the internal SMBus register bit and the external PCI_STOP# pin. 2 HW S2 Frequency Select Bit 2. Reflects the value of S2. This bit is Read-only. 1 HW S1 Frequency Select Bit 1. Reflects the value of S1. This bit is Read-only. 0 1 Reserved Byte 1: CPU Clock Register Bit @Pu p Name Description 7 1 6 0 CPUT1, CPUC1 CPUT/C Output Functionality Control when CPU_STOP# is asserted. CPUT2, CPUC2 0 = Drive CPUT to 6x IREF and drive CPUC LOW 1 = three-state all CPU outputs. This bit will override Byte0,Bit6 such that even if it is 0, when PD# goes LOW the CPU outputs will be three-stated. 5 0 CPUT2, CPUC2 CPUT/C2 Functionality Control when CPU_STOP# is asserted. 0 = Stopped LOW,1 = Free Running. This is a Read and Write control bit. 4 0 CPUT1, CPUC1 CPUT/C1 Functionality Control When CPU_STOP# is asserted. 0 = Stopped LOW, 1 = Free Running. This is a Read and Write control bit. 3 0 2 1 CPUT2, CPUC2 CPUT/C2 Output Control. 0 = disable, 1 = enabled. This is a Read and Write control bit. 1 1 CPUT1, CPUC1 CPUT/C1 Output Control. 0 = disable, 1 = enabled. This is a Read and Write control bit. 0 1 Reserved Reserved Reserved Notes: 3. PU = internal pull-up. PD = internal pull-down. T = tri-level logic input with valid logic voltages of LOW = < 0.8V, T = 1.0 – 1.8V and HIGH = > 2.0V. 4. The “Pin#” column lists the relevant pin number where applicable. The “@Pup” column gives the default state at power-up. Document #: 38-07507 Rev. *A Page 3 of 18 [+] Feedback CY28339 Byte 2:PCI Clock Control Register (all bits are Read and Write functional) Bi t @Pu p Nam e Description 7 0 REF REF Output Control. 0 = high strength, 1 = low strength. 6 1 PCI6 PCI6 Output Control. 0 = forced LOW, 1 = enabled 5 1 PCI5 PCI5 Output Control. 0 = forced LOW, 1 = enabled 4 1 PCI4 PCI4 Output Control. 0 = forced LOW, 1 = enabled 3 1 2 1 PCI2 PCI2 Output Control. 0 = forced LOW, 1 = enabled 1 1 PCI1 PCI1 Output Control. 0 = forced LOW, 1 = enabled 0 1 PCI0 PCI0 Output Control. 0 = forced LOW, 1 = enabled Reserved Byte 3: PCIF Clock and 48M Control Register (all bits are Read and Write functional) Bit @Pu p Name Description 7 1 DOT_48 M DOT_48M Output Control. 0 = forced LOW, 1 = enabled 6 1 USB_48 M USB_48M Output Control. 0 = forced LOW,1 = enabled 5 0 PCIF PCI_STOP# Control of PCIF. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. 4 1 PCI8 PCI_STOP# Control of PCI8. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. 3 1 PCI7 PCI_STOP# Control of PCI7. 0 = Free Running, 1 = Stopped when PCI_STOP# is asserted. 2 1 PCIF PCIF Output Control. 0 = forced LOW, 1 = running 1 1 PCI_8 PCI_8 Output Control. 0 = forced LOW, 1 = running 0 1 PCI_7 PCI_7 Output Control. 0 = forced LOW, 1 = running Byte 4: Control Register (all bits are Read and Write functional) Bit @Pup Name Description 7 0 SS2 Spread Spectrum Control Bit. 0 = down spread, 1 = center spread). 6 0 Reserved. Set = 0. 5 1 3V66_0 4 1 3V66_1/VCH 3 1 3V66_5 2 1 19 66BUFF2/3V66_4 Output Enable. 0 = disable, 1 = enabled 1 1 18 66BUFF1/3V66_3 Output Enable. 0 = disable, 1 = enabled 0 1 66BUFF0/3V66_2 66BUFF0/3V66_2 Output Enable. 0 = disable, 1 = enabled 3V66_0 Output Enable. 0 = disable, 1 = enabled 3V66_1/VCH Output Enable. 0 = disable, 1 = enabled 3V66_5 Output Enable. 0 = disable, 1 = enabled Byte 5:Clock Control Register (all bits are Read and Write functional) Bit @Pup 7 0 SS1 Spread Spectrum Control Bit. 6 1 SS0 Spread Spectrum Control Bit. 5 0 66IN to 66M delay Control MSB. 4 0 66IN to 66M delay Control LSB. 3 0 2 0 1 0 0 0 Document #: 38-07507 Rev. *A Name Description Reserved. Set = 0. DOT_48M DOT_48M Edge Rate Control. When set to 1, the edge is slowed by 15%. Reserved. Set = 0. USB_48M USB_48M edge rate control. When set to 1, the edge is slowed by 15%. Page 4 of 18 [+] Feedback CY28339 Byte 6: Silicon Signature Register[5] (all bits are Read-only) Bit @Pup 7 0 6 0 5 0 4 1 3 0 2 0 1 1 0 1 Name Description Revision = 0001 Vendor Code = 0011 Byte 7: Reserved Register Bit @Pup Name Description 7 0 Reserved. Set = 0. 6 0 Reserved. Set = 0. 5 0 Reserved. Set = 0. 4 0 Reserved. Set = 0. 3 0 Reserved. Set = 0. 2 0 Reserved. Set = 0. 1 0 Reserved. Set = 0. 0 0 Reserved. Set = 0. Byte 8: Dial-a-Frequency Control Register N Bit @Pup 7 0 Name Description Reserved. Set = 0. 6 0 N6, MSB 5 0 N5 4 0 N4 3 0 N3 2 0 N2 1 0 N3 0 0 N0, LSB These bits are for programming the PLL’s internal N register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. Byte 9: Dial-a-Frequency Control Register R Bit @Pup 7 0 Name Description Reserved. Set = 0. 6 0 R5, MSB 5 0 R4 4 0 R3 3 0 R2 2 0 R1 1 0 R0 0 0 DAF_ENB These bits are for programming the PLL’s internal R register. This access allows the user to modify the CPU frequency at very high resolution (accuracy). All other synchronous clocks (clocks that are generated from the same PLL, such as PCI) remain at their existing ratios relative to the CPU clock. R and N register mux selection. 0 = R and N values come from the ROM. 1 = data is loaded from DAF (SMBus) registers. Note: 5. When writing to this register, the device will acknowledge the Write operation, but the data itself will be ignored. Document #: 38-07507 Rev. *A Page 5 of 18 [+] Feedback CY28339 Dial-a-Frequency Features Special Functions SMBus Dial-a-Frequency feature is available in this device via Byte8 and Byte9. PCIF and IOAPIC Clock Outputs S(1:0) P 00 32005333 The PCIF clock outputs are intended to be used, if required, for systems IOAPIC clock functionality. Any two of the PCIF clock outputs can be used as IOAPIC 33-Mhz clock outputs. They are 3.3V outputs will be divided down via a simple resistive voltage divider to meet specific system IOAPIC clock voltage requirements. In the event that these clocks are not required, they can be used as general PCI clocks or disabled via the assertion of the PCI_STOP# pin. 01 48008000 3V66_1/VCH Clock Output 10 96016000 11 64010667 The 3V66_1/VCH pin has a dual functionality that is selectable via SMBus. P is a large-value PLL constant that depends on the frequency selection achieved through the hardware selectors (S1, S0). P value may be determined from Table 2. Table 2. P Value Configured as DRCG (66M), SMBus Byte0, Bit 5 = “0” Dial-a-dB Features SMBus Dial-a-dB feature is available in this device via Byte8 and Byte9. The default condition for this pin is to power-up in a 66M operation. In 66M operation this output is SSCG-capable and when spreading is turned on, this clock will be modulated. Spread Spectrum Clock Generation (SSCG) Configured as VCH (48M), SMBus Byte0, Bit 5 = “1” Spread Spectrum is a modulation technique used to minimizing EMI radiation generated by repetitive digital signals. A clock presents the greatest EMI energy at the center frequency it is generating. Spread Spectrum distributes this energy over a specific and controlled frequency bandwidth therefore causing the average energy at any one point in this band to decrease in value. This technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of EMI reduction). In this device, Spread Spectrum is enabled by setting specific register bits in the SMBus control bytes. Table 3 is a listing of the modes and percentages of Spread Spectrum modulation that this device incorporates. In this mode, output is configured as a 48-Mhz non-spread spectrum output that is phase-aligned with other 48M outputs (USB and DOT) to within 1-ns pin-to-pin skew. The switching of 3V66_1/VCH into VCH mode occurs at system power-on. When the SMBus Bit 5 of Byte 0 is programmed from a “0” to a “1,” the 3V66_1/VCH output may glitch while transitioning to 48M output mode. PD# (Power-down) Clarification SS2 SS1 SS0 Spread Mode Spread% 0 0 0 Down +0.00, –0.25 The PD# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. PD# is an asynchronous active LOW input. This signal is synchronized internally to the device powering down the clock synthesizer. PD# is an asynchronous function for powering up the system. When PD# is LOW, all clocks are driven to a LOW value and held there and the VCO and PLLs are also powered down. All clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the LOW “stopped” state. 0 0 1 Down +0.00, –0.50 PD# Assertion 0 1 0 Down +0.00, –0.75 0 1 1 Down +0.00, –1.00 1 0 0 Center +0.13, –0.13 1 0 1 Center +0.25, –0.25 1 1 0 Center +0.37, –0.37 1 1 1 Center +0.50, –1.50 When PD# is sampled LOW by two consecutive rising edges of the CPUC clock, then on the next HIGH-to-LOW transition of PCIF, the PCIF clock is stopped LOW. On the next HIGH-to-LOW transition of 66BUFF, the 66BUFF clock is stopped LOW. From this time, each clock will stop LOW on its next HIGH-to-LOW transition, except the CPUT clock. The CPU clocks are held with the CPUT clock pin driven HIGH with a value of 2 × Iref, and CPUC undriven. After the last clock has stopped, the rest of the generator will be shut down. Table 3. Spread Spectrum 3V66-0 Tpci PCI PCI_F Figure 1. Unbuffered Mode – 3V66_0 to PCI and PCIF Phase Relationship Document #: 38-07507 Rev. *A Page 6 of 18 [+] Feedback CY28339 PWRDWN# CPUT 133MHz CPUC 133MHz PCI 33MHz 3V66 USB 48MHz REF 14.318MHz Figure 2. Power-down Assertion Timing Waveforms – Unbuffered Mode 6 6 B u ff P C IF PW RDW N# CPU 133M Hz CPU# 133M Hz 3V66 6 6 In USB 48M Hz R E F 1 4 .3 1 8 M H z Figure 3. Power-down Assertion Timing Waveforms Figure – Buffered Mode Document #: 38-07507 Rev. *A Page 7 of 18 [+] Feedback CY28339 PD# Deassertion The power-up latency between PD# rising to a valid logic ‘1’ level and the starting of all clocks is less than 3.0 ms. 0.25mS Sample Inputs straps VDDA = 2.0V Wait for