CY28343OC

CY28343 Zero Delay SDR/DDR Clock Buffer Features • Phase-lock loop clock distribution for DDR and SDR SDRAM applications • One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs. • External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for SDR. Table 1. Function Table SELDDR_SDR# 1= DDR Mode CLKIN 2.5V Compatible 3.3V Compatible SDRAM(0:12) OFF DDRT/C(0:5) Active 2.5V Compatible OFF FBIN_DDR 2.5V Compatible OFF FBOUT_DDR Active 2.5V Compatible OFF FBIN_SDR FBOUT_SDR OFF OFF • External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR. • SMBus interface enables/disables outputs. • Conforms to JEDEC SDR/DDR specifications • Low jitter, low skew • 48 pin SSOP package 0 = SDRAM Mode Active 3.3V Compatible Active 3.3V Compatible Active 3.3V Compatible Block Diagram Pin Configuration[1] SCLK SDATA Control Logic VDD_2.5V FBOUT_DDR VDD_3.3V DDRT(0:5) DDRC(0:5) CLKIN FBIN_DDR VDD_3.3V FBOUT_SDR PLL *SELDDR_SDR FBIN_SDR SDRAM (0:12) VDD_3.3V SDRAM0 SDRAM1 SDRAM2 SDRAM3 VSS VDD_3.3V SDRAM4 SDRAM5 CLKIN SDRAM6 SDRAM7 VSS VDD_3.3V SDRAM8 SDRAM9 SDRAM10 SDRAM11 VSS VDD_3.3V SDRAM12 FBOUT_SDR FBIN_SDR* VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SELDDR_SDR#* FBIN_DDR* FBOUT_DDR VDD_2.5V DDRT5 DDRC5 DDRT4 DDRC4 VSS VDD_2.5 DDRT3 DDRC3 DDRT2 DDRC2 VSS VDD_2.5V DDRT1 DDRC1 DDRT0 DDRC0 VSS VDD_3.3V SCLK** SDATA** Note: 1. Pins marked with [*] have internal pull-down resistors. Pins marked with [**] have internal pull-up resistors. Cypress Semiconductor Corporation Document #: 38-07369 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 26, 2002 CY28343 Pin Description[2, 3] Pin 10 47 23 30,32,36,38 42,44 29,31,35,37 41,43 2-5,8,9 15-18,21 46 Name CLKIN FBIN_DDR FBIN_SDR DDRT(0:5) DDRC(0:5) SDRAM(0:12) FBOUT_DDR I/O I I PD I PD O O O O Clock Input. Reference the PLL Feedback Clock Output. Connect to FBOUT_DDR for accessing the PLL. See Function Table on page 1 Feedback Clock Input. Connect to FBOUT_SDR for accessing the PLL. See Function Table on page 1 Clock Outputs. True copies of the CLKIN input Clock Outputs. Complementary copies of the CLKIN input Clock Outputs. True copies of the CLKIN input Feedback Clock Output. Connect to FBIN_DDR for normal operation. A true copy of the CLKIN input. The delay of the PCB trace RC at this output will control Input Reference/DDR Output Clocks phase relationships. Feedback Clock Output. Connect to FBIN_SDR for normal operation. A true copy of the CLKIN input. The delay of the PCB trace RC at this output will control Input Reference/ SDR Output Clocks phase relationships. SDR or DDR Select Pin. See Function Table on page 1 Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 3.3V power supply for SDR outputs and two line serial Interface 2.5V power supply for DDR outputs Common Ground Description 22 FBOUT_SDR O 48 26 25 1,7,14,20,27 33,39,45 SELDDR_SDR# SCLK SDATA VDD_3.3V VDD_2.5V I PD I PU I/O PU 6,13,19,24,28 VSS ,34,40 Notes: 2. PU = internal pull-up PD = internal pull-down. 3. A bypass capacitor (0.1 mF) should be placed as close as possible to each positive power pin (