CY28351OC

CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the outputs to the clock input • Conforms to the DDRI specification • Spread Aware for electromagnetic interference (EMI) reduction • 48-pin SSOP package Description This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential outputs levels. This device is a zero delay buffer that distributes a clock input (CLKIN) to ten differential pairs of clock outputs (YT[0:9], YC[0:9]) and one feedback clock output (FBOUT). The clock outputs are individually controlled by the serial inputs SCLK and SDATA. The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for the test purposes. The PLL in this device uses the input clock (CLKIN) and the feedback clock (FBIN) to provide high-performance, low-skew, low-jitter output differential clocks. Block Diagram 10 Pin Configuration YT0 YC0 YT1 YC1 YT2 YC2 SCLK SDATA YT4 YC4 YT5 YC5 YT6 YC6 CLKIN PLL FBIN YT7 YC7 YT8 YC8 YT9 YC9 CY28351 Serial Interface Logic YT3 YC3 AVDD FBOUT VSS YC0 YT0 VDDQ YT1 YC1 VSS VSS YC2 YT2 VDD SCLK CLKIN NC VDDI AVDD AVSS VSS YC3 YT3 VDDQ YT4 YC4 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS YC5 YT5 VDDQ YT6 YC6 VSS VSS YC7 YT7 VDDQ SDATA NC FBIN VDDQ FBOUT NC VSS YC8 YT8 VDDQ YT9 YC9 VSS Cypress Semiconductor Corporation Document #: 38-07370 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised May 23, 2003 CY28351 Pin Description[1] Pin Number 13 35 3, 5, 10, 20, 22 46, 44, 39, 29, 27 2, 6, 9, 19, 23 47, 43, 40, 30, 26 33 Pin Name CLKIN FBIN YT(0:9) YC(0:9) FBOUT I/O I I O O O Clock Input. Feedback Clock Input. Connect to FBOUT for accessing the PLL. Clock Outputs. Clock Outputs. Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Output Pin Description Electrical Characteristics Input Input Differential Outputs 12 37 SCLK SDATA I I/O Serial Clock Input. Clocks data at SDATA into the Data Input for the two-line serial internal register. bus Serial Data Input. Input data is clocked to the Data Input and Output for the internal register to enable/disable individual outputs. two-line serial bus This provides flexibility in power management. 2.5V Power Supply for Logic. 2.5V Power Supply for Output Clock Buffers. 2.5V Power Supply for PLL. Common Ground. 2.5V Nominal 2.5V Nominal 2.5V Nominal 0.0V Ground 0.0V Analog Ground 11 4, 21, 28, 34, 38, 45 16 15 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 17 14, 32,36 VDD VDDQ AVDD VDDI VSS AVSS NC – 2.5V Power Supply for Two-line Serial Interface. 2.5V Nominal Analog Ground. Not Connected. Zero Delay Buffer When used as a zero delay buffer, the CY28351 will likely be in a nested clock tree application. For these applications the CY28351 offers a clock input as a PLL reference. The CY28351 then can lock onto the reference and translate with near zero delay to low skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes. Function Table Input VDDA GND GND 2.5V 2.5V 2.5V CLKIN L H L H < 20 MHz YT(0:9)[2] L H L H Hi-Z Outputs YC(0:9)[2] H L H L Hi-Z FBOUT L H L H Hi-Z PLL BYPASSED/OFF BYPASSED/OFF On On Off Notes: 1. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. 2. Each output pair can be three-stated via the two-line serial interface. Document #: 38-07370 Rev. *B Page 2 of 8 CY28351 Power Management The individual output enable/disable control of the CY28351 allows the user to implement unique power management schemes into the design. Outputs are three-stated when disabled through the two-line interface as individual bits are set LOW in Byte0 and Byte1 registers. The feedback output (FBOUT) cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. Byte0: Output Register 1 (1 = Enable, 0 = Disable) Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# 3, 2 5, 6 10, 9 20, 19 22, 23 46, 47 44, 43 39, 40 YT0, YC0 YT1, YC1 YT2, YC2 YT3, YC3 YT4, YC4 YT5, YC5 YT6, YC6 YT7, YC7 Description Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: • Command Code byte • Byte Count byte. Byte1: Output Register 2 (1 = Enable, 0 = Disable) Bit 7 6 5 4 3 2 1 0 Byte2: Test Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Pin# – – – – – – – – Reserved Reserved Reserved Reserved Reserved Reserved Reserved Description 0 = PLL leakage test, 1 = disable test @Pup 1 1 0 0 0 0 0 0 Pin# 29, 30 27, 26 – – – – – – YT8, YC8 YT9, YC9 Reserved Reserved Reserved Reserved Reserved Reserved Description Document #: 38-07370 Rev. *B Page 3 of 8 CY28351 Maximum Ratings[3] Input Voltage Relative to VSS:.............................. VSS – 0.3V Input Voltage Relative to VDDQ or AVDD: ............. VDD + 0.3V Storage Temperature: .................................–65°C to +150°C Operating Temperature: .................................... 0°C to +70°C Maximum Power Supply: ................................................3.5V This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, VIN and VOUT should be constrained to the range: VSS < (VIN or VOUT) < VDD. Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters VDD = VDDA = VDDQ = VDDI = 2.5V + 5%, TA = 0°C to +70°C[4] Parameter Description VIL Input Low Voltage VIH VIL VIH IIN IOL IOH VOL VOH VOUT VOC IOZ IDDQ IDSTAT IDD CIN Parameter fCLK tDC tLOCK Tr/Tf tpZL, tpZH tpLZ, tpHZ tCCJ tjit(h-per) tPLH tPHL tSKEW tPHASE tPHASEJ Input High Voltage Input Voltage Low Input Voltage High Input Current Output Low Current Output High Current Output Low Voltage Output High Voltage Output Voltage Swing[5] Output Crossing Voltage[6] High-Impedance Output Current Dynamic Supply Current[7] Static Supply Current PLL Supply Current Input Pin Capacitance VO = GND or VO = VDDQ All VDDQ and VDDI, FO = 170 MHz VDDA only Condition SDATA , SCLK SDATA , SCLK CLKIN, FBIN CLKIN, FBIN VIN = 0V or VIN = VDDQ, CLKT, FBIN VDDQ = 2.375V, VOUT = 1.2V VDDQ = 2.375V, VOUT= 1V VDDQ = 2.375V, IOL = 12 mA VDDQ = 2.375V, IOH = –12 mA Min. 2.2 0.4 2.1 –10 26 –18 1.7 VDDQ – 0.4 (VDDQ/2) VDDQ/2 (VDDQ/2) – 0.2 + 0.2 –10 10 235 9 4 300 1 12 6 1.1 35 –32 0.6 10 Typ. Max. 1.0 Unit V V V V µA mA mA V V V V µA mA mA mA pF AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to + 70°C[8,9] Description Operating Clock Frequency Input Clock Duty Cycle Maximum PLL lock Time Output Clocks Slew Rate Output Enable Time (all outputs)[10] Output Disable Time (all outputs)[10] Cycle to Cycle Jitter[12] Half-period jitter[12] LOW-to-HIGH Propagation Delay, CLKIN to YT HIGH-to-LOW Propagation Delay, CLKIN to YT Any Output to Any Output Skew[11] Phase Error[11] Phase Error Jitter f > 66 MHz f > 66 MHz f > 66 MHz –100 –100 1.5 1.5 –150 –50 3.5 3.5 20% to 80% of VOD Condition Min. Typ. Max. Unit 60 40 1 3 3 100 100 6 6 100 150 50 200 MHz 60 % 100 µs 2.5 V/ns ns ns ps ps ns ns ps ps ps Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. unused inputs must be held HIGH or LOW to prevent them from floating. 5. For load conditions, see Figure 7. 6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7. 7. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 7. 8. Parameters are guaranteed by design and characterization. Not 100% tested in production 9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz with a down spread of –0.5%. 10. Refers to transition of non-inverting output. 11. All differential input and output terminals are terminated with 120Ω/16 pF, as shown in Figure 7. 12. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. Document #: 38-07370 Rev. *B Page 4 of 8 CY28351 Parameter Measurement Information CLKIN 1.25V 1.25V FBIN 1.25V 1.25V t(∅)n t(∅)n+1 t(∅)n = CLKIN 1.25V Σ n1=N t(∅)n (N is large number of samples) Figure 1. Static Phase Offset 1.25V FBIN td(∅) t(∅) td(∅) td(∅) t(∅ ) td(∅) YT[0:9], FBOUT YC[0:9] YT[0:9], FBOUT YC[0:9] Figure 2. Dynamic Phase Offset tsk(o) Figure 3. Output Skew Document #: 38-07370 Rev. *B Page 5 of 8 CY28351 YT[0:9], FBOUT YC[0:9] tc(n) YT[0:9], FBOUT YC[0:9] 1 f(o) tjit(hper) = tc(n) - 1 fo Figure 4. Period Jitter YT[0:9], FBOUT YC[0:9] t(hper_n) 1 f(o) t(hper_N+1) tjit(hper) = thper(n) - 1 2x fo Figure 5. Half-Period Jitter YT[0:9], FBOUT YC[0: 9] t c(n) tjit(cc) = tc(n)-tc(n+1) Figure 6. Cycle-to-Cycle Jitter T PCB CLKT t c(n) M easurem ent Point 16 pF CLKIN 50 Ω CLKC FBIN 50 Ω FBO UT T PCB 110 Ω M easurem ent Point 16 pF Figure 7. Differential Signal Using Direct Termination Resistor Document #: 38-07370 Rev. *B Page 6 of 8 CY28351 Ordering Information Part Number CY28351OC CY28351OCT Package Type 48-pin SSOP 48-pin SSOP–Tape and Reel Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Package Drawing and Dimensions 48-lead Shrunk Small Outline Package O48 51-85061-*C Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07370 Rev. *B Page 7 of 8 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY28351 Document History Page Document Title: CY28351 Differential Clock Buffer/Driver, DDR400- and DDR333-Compliant Document Number: 38-07370 REV. ** *A *B ECN NO. 112786 122910 127011 Issue Date 05/08/02 12/26/02 05/28/03 Orig. of Change DMG RBI RGL New Data Sheet Description of Change Add power up requirements to maximum ratings information Change the maximum operating clock frequency from 170 MHz to 200 MHz Added DDR400- and DDR333-Compliant in the title. Document #: 38-07370 Rev. *B Page 8 of 8