CY28352OC

CY28352 Differential Clock Buffer/Driver DDR400and DDR333-Compliant Features • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop (PLL) clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to six differential outputs • External feedback pin FBIN is used to synchronize output to clock input • Conforms to DDRI specification • Spread Aware™ for electromagnetic interference (EMI) reduction • 28-pin SSOP package Description This PLL clock buffer is designed for 2.5-VDD and 2.5-AVDD operation and differential output levels. This device is a zero delay buffer that distributes a clock input CLKIN to six differential pairs of clock outputs (CLKT[0:5], CLKC[0:5]) and one feedback clock output FBOUT. The clock outputs are controlled by the input clock CLKIN and the feedback clock FBIN. The two-line serial bus can set each output clock pair (CLKT[0:5], CLKC[0:5]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes. The PLL in this device uses the input clock CLKIN and the feedback clock FBIN to provide high-performance, low-skew, low–jitter output differential clocks. Block Diagram Pin Configuration 10 SCLK SDATA Serial Interface Logic CLKT2 CLKC2 CLKT3 CLKC3 CLKIN NC AVDD AGND VDD CLKT2 CLKC2 CY28352 CLKT0 CLKC0 CLKT1 CLKC1 CLKC0 CLKT0 VDD CLKT1 CLKC1 GND SCLK CLKIN PLL FBIN CLKT4 CLKC4 CLKT5 CLKC5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND CLKC5 CLKT5 CLKC4 CLKT4 VDD SDATA NC FBIN FBOUT NC CLKT3 CLKC3 GND AVDD FBOUT 28 pin SSOP Cypress Semiconductor Corporation Document #: 38-07371 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised Sept. 02, 2004 CY28352 Pin Description[1] Pin Number Pin Name 8 CLKIN 20 FBIN I/O I I O O O I I/O Pin Description Complementary Clock Input. Feedback Clock Input. Connect to FBOUT for accessing the PLL. Clock Outputs Clock Outputs Feedback Clock Output. Connect to FBIN for normal operation. A bypass delay capacitor at this output will control Input Reference/Output Clocks phase relationships. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 2.5V Power Supply for Logic 2.5V Power Supply for PLL Ground Analog Ground for PLL Not Connected Output Electrical Characteristics Input Input Differential Outputs 2,4,13,17,24, CLKT(0:5) 26 1,5,14,16,25, CLKC(0:5) 27 19 7 22 3,12,23 10 6,15,28 11 9, 18, 21 FBOUT SCLK SDATA VDD AVDD GND AGND NC Data Input for the two line serial bus Data Input and Output for the two line serial bus 2.5V Nominal 2.5V Nominal Zero Delay Buffer When used as a zero delay buffer the CY28352 will likely be in a nested clock tree application. For these applications the CY28352 offers a clock input as a PLL reference. The CY28352 can then lock onto the reference and translate with near zero delay to low-skew outputs. For normal operation, the external feedback input, FBIN, is connected to the feedback output, FBOUT. By connecting the feedback output to the feedback input the propagation delay through the device is eliminated. The PLL works to align the output edge with the input reference edge thus producing a near zero delay. The reference frequency affects the static phase offset of the PLL and thus the relative delay between the inputs and outputs. When VDDA is strapped LOW, the PLL is turned off and bypassed for test purposes. Power Management The individual output enable/disable control of the CY28352 allows the user to implement unique power management schemes into the design. Outputs are three-stated when disabled through the two-line interface as individual bits are set low in Byte0 and Byte1 registers. The feedback output FBOUT cannot be disabled via two line serial bus. The enabling and disabling of individual outputs is done in such a manner as to eliminate the possibility of partial “runt” clocks. Function Table Inputs VDDA GND GND 2.5V 2.5V 2.5V CLKIN L H L H 66 MHz f > 66 MHz –100 –100 100 100 ps ps Notes: 3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 4. Unused inputs must be held HIGH or LOW to prevent them from floating. 5. For load conditions, see Figure 7. 6. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 7. 7. All outputs switching loaded with 16 pF in 60Ω environment. SeeFigure 7. 8. Parameters are guaranteed by design and characterization. Not 100% tested in production. 9. PLL is capable of meeting the specified parameters while supporting SSC synthesizers with modulation frequency between 30 kHz and 33.3 kHz, with a down spread of –0.5%. 10. Refers to transition of non-inverting output. 11. All differential input and output terminals are terminated with 120Ω/16 pF as shown in Figure 7. 12. Period Jitter and Half-Period Jitter specifications are separate, and must be met independently of each other. Document #: 38-07371 Rev. *C Page 4 of 8 CY28352 AC Parameters VDD = VDDQ = 2.5V ± 5%, TA = 0°C to +70°C (continued)[7, 9] Parameter tPLH tPHL tSKEW tPHASE tPHASEJ Description LOW-to-HIGH Propagation Delay, CLKIN to CLKT[0:5] HIGH-to-LOW Propagation Delay, CLKIN to CLKT[0:5] Any Output to Any Output Skew[11] Phase Error[11] Phase Error Jitter Condition Min. 1.5 1.5 Typ. 3.5 3.5 Max. 6 6 100 150 50 Unit ns ns ps ps ps f > 66 MHz –150 –50 Parameter Measurement Information CLKIN 1.25V 1.25V FBIN 1.25V 1.25V t(∅)n t(∅)n+1 t(∅)n = CLKIN 1.25V Σ n1=N t(∅)n (N is large number of samples) Figure 1. Static Phase Offset 1.25V FBIN td(∅) t(∅) td(∅) td(∅) t(∅ ) td(∅) Figure 2. Dynamic Phase Offset CLKT[0:5], FBOUT CLKC[0:5] CLKT[0:5], FBOUT CLKC[0:5] tsk(o) Figure 3. Output Skew Document #: 38-07371 Rev. *C Page 5 of 8 CY28352 CLKT[0:5], FBOUT CLKC[0:5] t c(n) CLKT[0:5], FBOUT CLKC[0:5] 1 f(o) t jit(hper) = t c(n) - 1 fo Figure 4. Period Jitter CLKT[0:5], FBO UT CLKC[0:5] t (hper_n) 1 f(o) t (hper_N+1) t jit(hper) = t hper(n) - 1 2 x fo Figure 5. Half-period Jitter C L K T[0:5], F B O U T C L K C [0:5] t c (n ) t jit(cc) = t c(n ) -t c (n + 1) t c(n) Figure 6. Cycle-to-Cycle Jitter T PCB C LKT 16 pF M easurem ent Point C LKIN 50 Ω C LKC FBIN 50 Ω FBO U T T PCB 110 Ω M easurem ent Point 16 pF Figure 7. Differential Signal Using Direct Termination Resistor Ordering Information Part Number CY28352OC CY28352OCT Lead-free CY28352OXC CY28352OXCT 28-pin SSOP 28-pin SSOP–Tape and Reel Commercial, 0° to 70°C Commercial, 0° to 70°C Package Type 28-pin SSOP 28-pin SSOP–Tape and Reel Product Flow Commercial, 0° to 70°C Commercial, 0° to 70°C Document #: 38-07371 Rev. *C Page 6 of 8 CY28352 Package Drawing and Dimensions 28-lead (5.3 mm) Shrunk Small Outline Package O28 51-85079-*C Spread Aware is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07371 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28352 Document History Page Document Title: CY28352 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant, Document Number: 38-07371 REV. ** *A *B *C ECN No. 112787 122911 127012 Issue Date 05/08/02 12/27/02 05/28/03 See ECN Orig. of Change DMG RBI RGL RGL New data sheet Add power-up requirements to maximum ratings information Change the maximum operating clock frequency from 170 MHz to 200 MHz Added DDR400- and DDR333-Compliant in the title. Added Lead-Free devices Description of Change Document #: 38-07371 Rev. *C Page 8 of 8