CY28443ZXC-2

PRELIMINARY CY28443-2 Clock Generator for Intel® Calistoga Chipset Features • Supports Intel® Pentium® M CPU • Selectable CPU frequencies • Differential CPU clock pairs • 100-MHz differential SRC clocks • 48-MHz USB clock • 96-MHz differential dot clock • Selectable 100-MHz LVDS clock • SRC clocks independently stoppable through CLKREQ#[A:B] CPU x2 / x3 SRC x5/6/7 PCI x6 REF x2 DOT96 x1 48M x1 SRC/LVDS100M x1 • 33-MHz PCI clock • Low-voltage frequency select input • I2C support with readback capabilities • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • 3.3V power supply • 56-pin package Block Diagram XIN XOUT SEL_CLKREQ PCI_STP# CPU_STP# CLKREQ[A:B]# ITP_SEL FS[C:A] 14.318M Hz Crystal PLL Reference VDD REF[0:1] IREF VDD CPUT[0:1] CPUC[0:1] VDD CPUT2_ITP/SRCT11 CPUC2_ITP/SRCC11 VDD SRCT([2:5],[8:9]) SRCC([2:5],[8:9]) VDD PCI[3:5] VDD_PCI PCIF[0:1] VDD SRCT0/100M T_SST SRCC0/100M C_SST VDD48 27MSpread VDD48 DOT96T DOT96C VDD48 48M 27M PLL VTT_PWRGD#/PD SDATA SCLK I2C Logic Pin Configuration VDD VSS PCI3 PCI4 PCI5/FCTSEL1 VSS VDD ITP_SEL/PCIF0 PCIF1 VTT_PWRGD#/PD VDD FSA /48M VSS DOT96T/27M non Spread DOT96C/27M Spread FSB SRCT0/100MT_SST SRCC0/100MC_SST SRCT2 SRCC2 VDD SRCT3 SRCC3 SRCT4 SRCC4 SRCT5 _SATA SRCC5_SATA VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PCI2/SEL_CLKREQ PCI_STP# CPU_STP# REF0/FSC REF1/FCTSEL0 VSS XIN XOUT VDD SDATA SCLK VSS CPUT0 CPUC0 VDD CPUT1 CPUC1 IREF VSSA VDDA SRCT11/CPUT2_itp SRCC11/CPUC2_itp VDD SRCT9/CLKREQA SRCC9/CLKREQB SRCT8 SRCC8 VSS CPU PLL Divider LVDS PLL FCTSEL1 Divider Fixed PLL Divider Divider VDD48 27MNon-spread Cypress Semiconductor Corporation Document #: 38-07718 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 17, 2005 PRELIMINARY Pin Descriptions Pin No. 1, 7, 11, 21, VDD 28, 34, 42, 48 2, 6, 13, 29, 45, 51 33,32 VSS SRCT9/CLKREQA#, SRCC9/CLKREQB# PCI[3:4] PCI5/FCTSEL1 ITP_EN/PCIF0 PCIF1 VTT_PWRGD#/PD Name Type PWR GND 3.3V power supply Ground Description CY28443-2 I/O, PU 3.3V LVTTL input for enabling assigned SRC clock (active LOW) or 100-MHz serial reference clock. Default function is SRC9 O, SE 33-MHz clock O, SE 33-MHz clock/3.3 LVTTL input for selecting SRC[T/C]0 or LVDS100M[T/C] (sampled on the VTT_PWRGD# assertion). I/O, SE 3.3V LVTTL input to enable SRC[T/C]7 or CPU[T/C]2_ITP/33-MHz clock output. (sampled on the VTT_PWRGD# assertion). I/O, SE 33-MHz clock I, PU 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_[C:A], ITP_EN, FCTSEL[1:0], SEL_CLKREQ. After VTT_PWRGD# (active LOW) assertion, this pin becomes a real-time input for asserting power-down (active HIGH). 3.3V-tolerant input for CPU frequency selection/Fixed 48-MHz clock output. 3,4 5 8 9 10 12 14, 15 FSA/48M DOT96T/27M non Spread DOT96C/27M Spread FSB SRC[T/C]0/ LCD100M[T/C] I/O O, DIF Fixed 96-MHz Differential clock/Single-ended 27-MHz clocks. When configured for 27 MHz, only the clock on pin 15 contains spread. I 3.3V-tolerant input for CPU frequency selection. 16 17,18 O,DIF 100-MHz Differential Serial Reference clock/100-MHz LVDS Differential clock O, DIF 100-MHz Differential Serial Reference clocks. O, DIF Differential serial reference clock. Recommended output for SATA. 19,20,22,23, SRCT/C 24,25,30,31 26,27 36,35 37 38 39 44,43,41,40 46 47 49 50 52 53 54 55 56 SRC[T/C]5_SATA CPUT2_ITP/SRCT11, O, DIF Selectable differential CPU or SRC clock output. CPUC2_ITP/SRCC11 VDDA VSSA IREF CPU[T/C][0:1] SCLK SDATA XOUT XIN REF1 REF0/FSC CPU_STP# PCI_STP# PCI2/SEL_CLKREQ PWR GND I 3.3V power supply for PLL. Ground for PLL. A precision resistor is attached to this pin, which is connected to the internal current reference. SMBus-compatible SCLOCK. SMBus-compatible SDATA. 14.318-MHz crystal input. Fixed 14.318-MHz clock output 3.3V-tolerant input for CPU frequency selection/fixed 14.318 clock output. 3.3V LVTTL input for CPU_STP# active LOW. 3.3V LVTTL input for PCI_STP# active LOW. O, DIF Differential CPU clock outputs. I I/O I O I/O I, PU I, PU O, SE 14.318-MHz crystal output. I/O, PD Fixed 33-MHz clock output/3.3V-tolerant input for CLKREQ pin selection (sampled on the VTT_PWRGD# assertion). 0 = CLKREQ[A:B]# functionality 1 = SRC[T/C]9 functionality Document #: 38-07718 Rev. *B Page 2 of 24 PRELIMINARY Table 1. Frequency Select Table FSA, FSB and FSC FSC 1 0 0 0 FSB 0 0 1 1 FSA 1 1 1 0 CPU 100 MHz 133 MHz 166 MHz 200 MHz SRC 100 MHz 100 MHz 100 MHz 100 MHz PCIF/PCI 33 MHz 33 MHz 33 MHz 33 MHz 27MHz 27 MHz 27 MHz 27 MHz 27 MHz REF0 14.318 MHz 14.318 MHz 14.318 MHz 14.318 MHz DOT96 CY28443-2 USB 48 MHz 48 MHz 48 MHz 48 MHz 96 MHz 96 MHz 96 MHz 96 MHz Frequency Select Pins (FSA, FSB, and FSC) Host clock frequency selection is achieved by applying the appropriate logic levels to FSA, FSB, FSC inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FSA, FSB, and FSC input values. For all logic levels of FSA, FSB, and FSC, VTT_PWRGD# employs a one-shot functionality in that once a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FSA, FSB, and FSC transitions will be ignored, except in test mode. initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. Data Protocol The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Serial Data Interface To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 36:29 37 45:38 46 .... .... .... Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Byte Count – 8 bits (Skip this step if I2C_EN bit set) Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits Acknowledge from slave Data Byte /Slave Acknowledges Data Byte N –8 bits Acknowledge from slave Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 46:39 47 55:48 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeat start Slave address – 7 bits Read = 1 Acknowledge from slave Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits Block Read Protocol Description Document #: 38-07718 Rev. *B Page 3 of 24 PRELIMINARY Table 3. Block Read and Block Write Protocol (continued) Block Write Protocol Bit .... Stop Description Bit 56 .... .... .... .... Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 9 10 18:11 19 27:20 28 29 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Data byte – 8 bits Acknowledge from slave Stop Description Bit 1 8:2 9 10 18:11 19 20 27:21 28 29 37:30 38 39 Start Slave address – 7 bits Write Acknowledge from slave Command Code – 8 bits Acknowledge from slave Repeated start Slave address – 7 bits Read Acknowledge from slave Data from slave – 8 bits NOT Acknowledge Stop Byte Read Protocol Acknowledge Block Read Protocol CY28443-2 Description Data bytes from slave / Acknowledge Data Byte N from slave – 8 bits NOT Acknowledge Stop Description Document #: 38-07718 Rev. *B Page 4 of 24 PRELIMINARY Control Registers Byte 0: Control Register 0 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name RESERVED RESERVED SRC[T/C]5 SRC[T/C]4 SRC[T/C]3 SRC[T/C]2 RESERVED SRC[T/C]0 /100M[T/C]_SST Description RESERVED RESERVED SRC[T/C]5 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]4 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]3 Output Enable 0 = Disable (Tri-state), 1 = Enable SRC[T/C]2 Output Enable 0 = Disable (Tri-state), 1 = Enable RESERVED, Set = 1 SRC[T/C]0 /100M[T/C]_SST Output Enable 0 = Disable (Hi-Z), 1 = Enable CY28443-2 Byte 1: Control Register 1 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 0 Name PCIF0 27M_nss_DOT_96[T/C] USB_48MHz REF0 REF1 CPU[T/C]1 CPU[T/C]0 CPU, SRC, PCI, PCIF spread enable PCIF0 Output Enable 0 = Disabled, 1 = Enabled 27M nonspread and DOT_96 MHz Output Enable 0 = Disable (Tri-state), 1 = Enabled USB_48M MHz Output Enable 0 = Disabled, 1 = Enabled REF0 Output Enable 0 = Disabled, 1 = Enabled REF1 Output Enable 0 = Disabled, 1 = Enabled CPU[T/C]1 Output Enable 0 = Disable (Tri-state), 1 = Enabled CPU[T/C]0 Output Enable 0 = Disable (Tri-state), 1 = Enabled PLL1 (CPU PLL) Spread Spectrum Enable 0 = Spread off, 1 = Spread on Description Byte 2: Control Register 2 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name PCI5 PCI4 PCI3 PCI2 RESERVED RESERVED CPU[T/C]2 PCIF1 PCI5 Output Enable 0 = Disabled, 1 = Enabled PCI4 Output Enable 0 = Disabled, 1 = Enabled PCI3 Output Enable 0 = Disabled, 1 = Enabled PCI2 Output Enable 0 = Disabled, 1 = Enabled RESERVED RESERVED CPU[T/C]2 Output Enable 0 = Disabled (Hi-Z), 1 = Enabled PCIF1 Output Enable 0 = Disabled, 1 = Enabled Description Document #: 38-07718 Rev. *B Page 5 of 24 PRELIMINARY Byte 3: Control Register 3 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 0 0 0 0 0 Name RESERVED RESERVED SRC5 SRC4 SRC3 SRC2 RESERVED SRC0 RESERVED, Set = 0 RESERVED, Set = 0 Description CY28443-2 Allow control of SRC[T/C]5 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]4 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]3 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]2 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 0 Allow control of SRC[T/C]0 with assertion of PCI_STP# or SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Byte 4: Control Register 4 Bit 7 6 5 4 3 2 1 0 @Pup 0 0 1 0 0 1 1 1 Name 100M[T/C]_SST DOT96[T/C] SRC[T/C] PCIF1 PCIF0 CPU[T/C]2 CPU[T/C]1 CPU[T/C]0 Description 100M[T/C]_SST PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state DOT PWRDWN Drive Mode 0 = Driven in PWRDWN, 1 = Tri-state SRC[T/C] Stop Drive Mode when CLKREQ# asserted 0 = Driven, 1 = Tri-state Allow control of PCIF1 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of PCIF0 with assertion of SW and HW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of CPU[T/C]2 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]1 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Allow control of CPU[T/C]0 with assertion of CPU_STP# 0 = Free running, 1 = Stopped with CPU_STP# Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C] Description SRC[T/C] Stop Drive Mode 0 = Driven when PCI_STP# asserted, 1 = Tri-state when PCI_STP# asserted CPU[T/C]2 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted CPU[T/C]1 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted CPU[T/C]0 Stop Drive Mode 0 = Driven when CPU_STP# asserted, 1 = Tri-state when CPU_STP# asserted SRC[T/C] PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted CPU[T/C]2 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted 6 0 CPU[T/C]2 5 0 CPU[T/C]1 4 0 CPU[T/C]0 3 2 0 0 SRC[T/C] CPU[T/C]2 Document #: 38-07718 Rev. *B Page 6 of 24 PRELIMINARY Byte 5: Control Register 5 (continued) Bit 1 0 @Pup 0 0 Name CPU[T/C]1 CPU[T/C]0 Description CY28443-2 CPU[T/C]1 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted CPU[T/C]0 PWRDWN Drive Mode 0 = Driven when PD asserted, 1 = Tri-state when PD asserted Byte 6: Control Register 6 Bit 7 6 5 4 3 @Pup 0 0 1 1 1 Name TEST_SEL TEST_MODE REF1 REF0 REF/N or Tri-state Select 0 = Tri-state, 1 = REF/N Clock Test Clock Mode Entry Control 0 = Normal operation, 1 = REF/N or Tri-state mode, REF0 Output Drive Strength 0 = Low, 1 = High REF0 Output Drive Strength 0 = Low, 1 = High Description PCI, PCIF and SRC clock SW PCI_STP Function outputs except those set 0 = SW PCI_STP assert, 1 = SW PCI_STP deassert When this bit is set to 0, all STOPPABLE PCI, PCIF, and SRC outputs will to free running be stopped in a synchronous manner with no short pulses. When this bit is set to 1, all STOPPED PCI, PCIF, and SRC outputs will resume in a synchronous manner with no short pulses. FSC FSB FSA FSC Reflects the value of the FSC pin sampled on power-up 0 = FSC was low during VTT_PWRGD# assertion FSB Reflects the value of the FSB pin sampled on power-up 0 = FSB was low during VTT_PWRGD# assertion FSA Reflects the value of the FSA pin sampled on power-up 0 = FSA was low during VTT_PWRGD# assertion 2 1 0 HW HW HW Byte 7: Vendor ID Bit 7 6 5 4 3 2 1 0 @Pup 0 0 0 1 1 0 0 0 Name Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Revision Code Bit 3 Revision Code Bit 2 Revision Code Bit 1 Revision Code Bit 0 Vendor ID Bit 3 Vendor ID Bit 2 Vendor ID Bit 1 Vendor ID Bit 0 Description Byte 8: Control Register 8 Bit 7 6 5 4 3 2 @Pup 0 0 0 0 0 1 CPU_SS CPU-DWN_SS RESERVED RESERVED RESERVED 48M Name 0:–0.5% (Peak to peak) 1: –1.0% (Peak to peak) 0: Down Spread 1: Center Spread RESERVED, Set = 0 RESERVED, Set = 0 RESERVED, Set = 0 48-MHz Output Drive Strength 0 = Low, 1 = High Page 7 of 24 Description Document #: 38-07718 Rev. *B PRELIMINARY Byte 8: Control Register 8 (continued) Bit 1 0 @Pup 1 1 PCIF0 Name RESERVED RESERVED, Set = 1 33-MHz Output Drive Strength 0 = Low, 1 = High Description CY28443-2 Byte 9: Control Register 9 Bit 7 6 5 4 @Pup 0 0 0 0 S3 S2 S1 S0 Name Description 27_96_100_SSC Spread Spectrum Selection table: S[3:0] SS% ‘0000’ = –0.5%(Default value) ‘0001’ = –1.0% ‘0010’ = –1.5% ‘0011’ = –2.0% ‘0100’ = ±0.25% ‘0101’ = ±0.5% ‘0110’ = ±0.75% ‘0111’ = ±1.0% ‘1000’ = –0.35% ‘1001’ = –0.68% ‘1010’ = –1.09% ‘1011’ = –1.425% ‘1100’ = ±0.17% ‘1101’ = ±0.34% ‘1110’ = ±0.545% ‘1111’ = ±0.712% 3 2 1 0 1 1 1 1 RESERVED 27M Spread 27M_SS/LCD100M Spread Enable PCIF1 RESERVED, Set = 1 27-MHz Spread Output Enable 0 = Disable (Hi-Z), 1 = Enable 27M_SS/LCD100M Spread spectrum enable. 0 = Disable, 1 = Enable. 33-MHz Output Drive Strength 0 = Low, 1 = High Byte 10: Control Register 10 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 0 0 0 0 Name SRC[T/C]11 SRC[T/C]9 RESERVED SRC[T/C]8 SRC[T/C]9 SRC[T/C]11 RESERVED SRC[T/C]8 SRC[T/C]11 Output Enable 0 = Disable (Hi-Z), 1 = Enable SRC[T/C]9 Output Enable 0 = Disable (Hi-Z), 1 = Enable RESERVED, Set = 1 SRC[T/C]8 Output Enable 0 = Disable (Hi-Z), 1 = Enable Allow control of SRC[T/C]9 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Allow control of SRC[T/C]11 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# RESERVED, Set = 0 Allow control of SRC[T/C]8 with assertion of SW PCI_STP# 0 = Free running, 1 = Stopped with PCI_STP# Page 8 of 24 Description Document #: 38-07718 Rev. *B PRELIMINARY Byte 11: Control Register 11 Bit 7 6 5 4 3 2 1 0 @Pup 0 HW HW HW 0 0 0 HW Name RESERVED RESERVED RESERVED RESERVED 27MHz RESERVED RESERVED RESERVED RESERVED Set = 0 RESERVED RESERVED RESERVED Description CY28443-2 27 MHz (spread and non-spread) Output Drive Strength 0 = Low, 1 = High RESERVED Set = 0 RESERVED Set = 0 RESERVED Byte 12: Control Register 12 Bit 7 6 5 4 3 2 1 0 @Pup 0 1 1 1 1 1 1 1 Name CLKREQ#A CLKREQ#B RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED CLKREQ#A Enable 0 = Disable 1 = Enable CLKREQ#B Enable 0 = Disable 1 = Enable RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED Description Byte 13: Control Register 13 Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 Name RESERVED 96/100M Clock Speed RESERVED RESERVED PCI5 PCI4 PCI3 PCI2 RESERVED 96/100 SRC Clock Speed 0 = 96 MHz 1 = 100 MHz RESERVED, Set = 1 RESERVED, Set = 1 PCI5 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High PCI4 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High PCI3 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High PCI2 (Spread and Non-spread) Output Drive Strength 0 = Low, 1 = High Description Byte 14: Control Register 14 Bit 7 6 5 4 @Pup 1 0 0 0 Name RESERVED RESERVED RESERVED CLKREQ#A RESEREVD RESERVED RESERVED SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#A 1 = SRC[T/C]5 stoppable by CLKREQ#A Description Document #: 38-07718 Rev. *B Page 9 of 24 PRELIMINARY Byte 14: Control Register 14 (continued) Bit 3 @Pup 0 Name CLKREQ#A Description SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#A 1 = SRC[T/C]4 stoppable by CLKREQ#A SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#A 1 = SRC[T/C]3 stoppable by CLKREQ#A SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#A 1 = SRC[T/C]2 stoppable by CLKREQ#A SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#A 1 = SRC[T/C]1 stoppable by CLKREQ#A CY28443-2 2 0 CLKREQ#A 1 0 CLKREQ#A 0 0 CLKREQ#A Byte 15: Control Register 15 Bit 7 @Pup 1 Name CLKREQ#B Description SRC[T/C]8 Control 0 = SRC[T/C]8 not stoppable by CLKREQ#B 1 = SRC[T/C]8 stoppable by CLKREQ#B RESERVED RESERVED SRC[T/C]5 Control 0 = SRC[T/C]5 not stoppable by CLKREQ#B 1= SRC[T/C]5 stoppable by CLKREQ#B SRC[T/C]4 Control 0 = SRC[T/C]4 not stoppable by CLKREQ#B 1= SRC[T/C]4 stoppable by CLKREQ#B SRC[T/C]3 Control 0 = SRC[T/C]3 not stoppable by CLKREQ#B 1= SRC[T/C]3 stoppable by CLKREQ#B SRC[T/C]2 Control 0 = SRC[T/C]2 not stoppable by CLKREQ#B 1= SRC[T/C]2 stoppable by CLKREQ#B SRC[T/C]1 Control 0 = SRC[T/C]1 not stoppable by CLKREQ#B 1= SRC[T/C]1 stoppable by CLKREQ#B 6 5 4 0 0 0 RESERVED RESERVED CLKREQ#B 3 0 CLKREQ#B 2 0 CLKREQ#B 1 0 CLKREQ#B 0 0 CLKREQ#B Table 5. Crystal Recommendations Frequency (Fund) 14.31818 MHz Cut AT Loading Load Cap Parallel 20 pF Drive (max.) 0.1 mW Shunt Cap (max.) 5 pF Motional (max.) 0.016 pF Tolerance (max.) 35 ppm Stability (max.) 30 ppm Aging (max.) 5 ppm The CY28443-2 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28443-2 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance Document #: 38-07718 Rev. *B Page 10 of 24 PRELIMINARY CY28443-2 Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe Figure 1. Crystal Capacitive Clarification = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. C lock C hip CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) CLK_REQ[0:1]# Description The CLKREQ#[A:B] signals are active LOW inputs used for clean enabling and disabling selected SRC outputs. The outputs controlled by CLKREQ#[A:B] are determined by the settings in register byte 8. The CLKREQ# signal is a de-bounced signal in that its state must remain unchanged during two consecutive rising edges of SRCC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[A:B]# Assertion (CLKREQ# -> LOW) C i1 Ci2 Pin 3 to 6p Cs1 X1 X2 Cs2 Trace 2.8 pF XTAL Ce1 C e2 Trim 33 pF All differential outputs that were stopped are to resume normal operation in a glitch-free manner. The maximum latency from the assertion to active outputs is between 2–6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. All stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] deassertion to a voltage greater than 200 mV. CLK_REQ[A:B]# Deassertion (CLKREQ# -> HIGH) The impact of deasserting the CLKREQ#[A:B] pins is all SRC outputs that are set in the control registers to stoppable via deassertion of CLKREQ#[A:B] are to be stopped after their next transition. The final state of all stopped DIF signals is LOW, both SRCT clock and SRCC clock outputs will not be driven. Figure 2. Crystal Loading Example CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[A:B] Deassertion/Assertion Waveform Document #: 38-07718 Rev. *B Page 11 of 24 PRELIMINARY PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual-function pin. During initial power-up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled LOW by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active HIGH input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted HIGH, all clocks need to be driven to a LOW value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) Assertion When PD is sampled HIGH by two consecutive rising edges of CPUC, all single-ended outputs will be held LOW on their next HIGH-to-LOW transition and differential clocks must held high or tri-stated (depending on the state of the control register drive mode bit) on the next diff clock# HIGH-to-LOW transition within 4 clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF CY28443-2 to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are tri-state. Note Figure 4 shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100, 133, 166, and 200 MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 µs after asserting Vtt_PwrGd#. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 µs of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Figure 5 is an example showing the relationship of clocks coming up. It should be noted that 96_100_SSC will follow the DOT waveform is selected for 96 MHz and the SRC waveform when in 100-MHz mode. Figure 4. Power-down Assertion Timing Waveform Tstable 200 mV Figure 7. CPU_STP# Deassertion Waveform 1.8 ms CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 8. CPU_STP#= Driven, CPU_PD = Driven, DOT_PD = Driven Document #: 38-07718 Rev. *B Page 13 of 24 PRELIMINARY CY28443-2 1.8 ms CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) DOT96T DOT96C Figure 9. CPU_STP# = Tri-state, CPU_PD = Tri-state, DOT_PD = Tri-state PCI_STP# Assertion The PCI_STP# signal is an active LOW input used for synchronous stopping and starting the PCI outputs while the rest of the clock generator continues to function. The set-up time for capturing PCI_STP# going LOW is 10 ns (tSU). (See Figure 10.) The PCIF clocks will not be affected by this pin if their corresponding control bit in the SMBus register is set to allow them to be free running. Tsu PCI_STP# Deassertion The deassertion of the PCI_STP# signal will cause all PCI and stoppable PCIF clocks to resume running in a synchronous manner within two PCI clock periods after PCI_STP# transitions to a HIGH level. PCI_STP# PCI_F PCI SRC 100MHz Figure 10. PCI_STP# Assertion Waveform Tsu Tdrive_SRC PCI_STP# PCI_F PCI SRC 100MHz Figure 11. PCI_STP# Deassertion Waveform Document #: 38-07718 Rev. *B Page 14 of 24 PRELIMINARY CY28443-2 FS_A, FS_B,FS_C VTT_PWRGD# PWRGD_VRM VDD Clock Gen Clock State State 0 0.2-0.3 ms Delay State 1 Wait for VTT_PWRGD# Sample Sels State 2 State 3 Device is not affected, VTT_PWRGD# is ignored Clock Outputs Off On Clock VCO Off On Figure 12. VTT_PWRGD# Timing Diagram S1 VTT_PWRGD# = Low S2 Delay >0.25 ms Sample Inputs straps VDD_A = 2.0V Wait for