CY28RS400OXC

CY28RS400 Clock Generator for ATI RS400 Chipset Features • Low-voltage frequency select input • I2C support with readback capabilities • Supports Intel CPU • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Selectable CPU frequencies • Differential CPU clock pairs • 3.3V power supply • 100-MHz differential SRC clocks • 56-pin SSOP and TSSOP packages • 48-MHz USB clock • 33-MHz PCI clock Block Diagram XIN XOUT CPU_STP# CLKREQ[0:1]# XTAL OSC PLL1 SRC PCI REF USB_48 x3 x8 x1 x3 x1 Pin Configuration VDD_REF REF[0:2] Divider Network IREF PD PLL2 I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28RS400 Xin XOUT VDD_48 VDD_CPU USB_48 CPUT[0:2], CPUC[0:2], VSS_48 VDD_SRC VTT_PWRGD#/PD SRCT[0:5],SRCC[0:5] SCLK SDATA VDD_SRCS SRCST[0:1],SRCSC[0:1] FSC CLKREQ#0 VDD_PCI CLKREQ#1 PCI SRCT5 SRCC5 VDD_SRC VSS_SRC VDD_48 MHz SRCT4 SRCC4 SRCT3 USB_48 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1 PLL Ref Freq FS_[C:A] VTT_PWRGD# SDATA SCLK CPU 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_REF VSS_REF REF0/FSA REF1/FSB REF2 VDD_PCI PCI0/409_410 VSS_PCI CPU_STOP# CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 CPUT2 CPUC2 VDDA VSSA IREF VSS_SRC1 VDD_SRC1 SRCT0 SRCC0 VDD_SRCS VSS_SRCS SRCST0 SRCSC0 56 SSOP/TSSOP Cypress Semiconductor Corporation Document #: 38-07637 Rev. *B • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised October 19, 2004 [+] Feedback CY28RS400 Pin Description Pin No. Name 47,46,43,42, 41,40 CPUT/C[2:0] 50 PCI0/409_410 I/O, PD 37 IREF I 54 REF0/ FSA I/O, SE, 14.318MHz REF clock ouput/ CPU Frequency Select. Intel Type-5 buffer. 53 REF1/FSB I/O, SE 14.318MHz REF clock ouput/ CPU Frequency Select. Intel Type-5 buffer. 52 REF2 7 SCLK 8 SDATA 27, 28, 30, 29 SRCST/C[1:0] 12, 13, 16, 17, 18, 19, 22, 23, 24, 25 ,34,33 SRCT/C[5:0] 10,11 CLKREQ#[0:1] Type Description O, DIF Differential CPU clock output. Intel Type-X buffer. 33-MHz clock output/CPU Frequency table Select Intel Type-5 buffer. 0 = 410 frequency select table 1 = 409 frequency select table. This has an internal pull-down A precision resistor attached to this pin is connected to the internal current reference. O, SE 14.318MHz REF clock ouput. Intel Type-5 buffer. I,PU SMBus-compatible SCLOCK.This pin has an internal pullup, but is tri-stated in power-down. I/O, PU SMBus compatible SDATA.This pin has an internal pullup, but is tri-stated in power-down. O, DIF Differential Selectable Serial reference clock. Intel Type-X buffer. Includes overclock support through SMBUS O, DIF 100 MHz Differential Serial reference clock. Intel Type-X buffer. I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard PD specification. These pins have an internal pull-down. 0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled 4 USB_48 6 VTT_PWRGD#/PD O, SE 48-MHz clock output. Intel Type-3A buffer. I PD 3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B, FS_C and 409_410 inputs. After asserting VTT_PWRGD# (active low), this pin becomes a realtime input for asserting power down (active high) 48 CPU_STP# I, PU 3.3V LVTTL input. This pin is used to gate the CPU outputs. CPU outputs are turned off two cycles after assertion of this pin 9 FSC I 3 VDD_48 PWR 3.3V LVTTL input. CPU Clock Frequency Select 45 VDD_CPU PWR 3.3V power supply for CPU outputs 51 VDD_PCI PWR 3.3V power supply for PCI outputs 56 VDD_REF PWR 3.3V power supply for REF outputs 14, 21 VDD_SRC PWR 3.3V power supply for SRC outputs 35 VDD_SRC1 PWR 3.3V power supply for SRC outputs 32 VDD_SRCS PWR 3.3V power supply for SRCS outputs 39 VDDA PWR 3.3V Analog Power for PLLs 5 VSS_48 GND Ground for USB outputs 44 VSS_CPU GND Ground for CPU outputs 49 VSS_PCI GND Ground for PCI outputs 3.3V power supply for USB outputs 55 VSS_REF GND Ground for REF outputs 15, 20, 26 VSS_SRC GND Ground for SRC outputs 36 VSS_SRC1 GND Ground for SRC outputs 31 VSS_SRCS GND Ground for SRCS outputs 38 VSSA GND 1 XIN I 14.318-MHz Crystal Input 2 XOUT O 14.318-MHz Crystal Output Document #: 38-07637 Rev. *B Analog Ground Page 2 of 19 [+] Feedback CY28RS400 Frequency Select Pins (FS_A, FS_B, FS_C and 409_410) a valid low on VTT_PWRGD# has been sampled, all further VTT_PWRGD#, FS_A, FS_B, FS_C and 409-410 transitions will be ignored. There are 2 CPU frequency select tables. One based on the CK409 specifications and one based on the CK410 specifications. The table to be used is determined by the value latched on the PCI0/409_410 pin by the VTT_PWRGD/PD# pin. A '0' on this pin selects the 410 frequency table and a '1' on this pin selects the 409 frequency table. In the 409 table, only the FS_A and FS_B pins influence the frequency selection. Host clock frequency selection is achieved by applying the appropriate logic levels to FS_A, FS_B, FS_C and 409_410 inputs prior to VTT_PWRGD# assertion (as seen by the clock synthesizer). Upon VTT_PWRGD# being sampled low by the clock chip (indicating processor VTT voltage is stable), the clock chip samples the FS_A, FS_B, FS_C and 409_410 input values. For all logic levels of FS_A, FS_B, FS_C and 409_410 VTT_PWRGD# employs a one-shot functionality in that once Table 1. Frequency Select Table (FS_A FS_B FS_C) 410 mode, 409_410 = 0 FS_C FS_B FS_A CPU SRC PCIF/PCI REF0 USB 1 0 1 100 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz 0 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz 0 1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz 0 0 0 266 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz 1 1 1 Reserved 100 MHz 33 MHz 14.318 MHz 48 MHz Table 2. Frequency Select Table (FS_A FS_B) 410 mode, 409_410 = 1 FS_B FS_A CPU SRC PCIF/PCI REF0 USB 0 0 100 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz 0 1 133 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz 1 0 200 MHz 100 MHz 33 MHz 14.318 MHz 48 MHz Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 3. Table 3. Command Code Definition Bit 7 The block write and block read protocol is outlined in Table 4 while Table 5 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:5) Chip select address, set to ‘00’ to access device (4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' Table 4. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write Block Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits 19 Acknowledge from slave 19 Acknowledge from slave Document #: 38-07637 Rev. *B Page 3 of 19 [+] Feedback CY28RS400 Table 4. Block Read and Block Write Protocol (continued) Block Write Protocol Bit 27:20 28 36:29 37 45:38 Description Byte Count – 8 bits Block Read Protocol Bit 20 Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N –8 bits .... Acknowledge from slave .... Stop 27:21 Description Repeat start Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge Table 5. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 8:2 Slave address – 7 bits 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 18:11 Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeated start 19 27:20 28 Acknowledge from slave 29 Stop Document #: 38-07637 Rev. *B 9 Description Start 27:21 Write Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Page 4 of 19 [+] Feedback CY28RS400 Control Registers Byte 0:Control Register 0 Bit @Pup Name Description 7 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC [T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 SRCS[T/C]1 SRCS[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 SRCS[T/C]0 SRCS[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name Description 7 1 REF2 REF2 Output Enable 0 = Disable, 1 = Enable 6 1 REF1 REF1 Output Enable 0 = Disable, 1 = Enable 5 1 REF0 REF0 Output Enable 0 = Disable, 1 = Enable 4 1 PCI0 PCI0 Output Enable 0 = Disable, 1 = Enable 3 1 USB_48 2 1 CPU[T/C]2 CPU[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable USB_48MHz Output Enable 0 = Disable, 1 = Enable Byte 2: Control Register 2 Bit @Pup Name 7 1 CPUT/C SRCT/C Spread Spectrum Selection ‘0’ = -0.35% ‘1’ = -0.50% 6 1 USB_48 48MHz Output Drive Strength 0 = 1x, 1 = 2x 5 1 PCI 33MHz Output Drive Strength 0 = 1x, 1 = 2x 4 0 Reserved Reserved 3 1 Reserved Reserved 2 0 CPU SRC 1 1 Reserved Document #: 38-07637 Rev. *B Description CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Reserved Page 5 of 19 [+] Feedback CY28RS400 Byte 2: Control Register 2 (continued) Bit @Pup Name 0 1 Reserved Description Reserved Byte 3: Control Register 3 Bit @Pup Name 7 1 CLKREQ# Description 6 0 CPU CPU pd drive mode 0 = CPU clocks driven when power down, 1 = CPU clocks tri-state 5 1 SRC SRC pd drive mode 0 = SRC clocks driven when power down, 1 = SRC clocks tri-state 4 0 CPU CPU_STOP# drive mode 0 = CPU clocks driven , 1 = CPU clocks tri-state 3 1 CPU2 Allow control of CPU2 with CPU_STOP# 0 = CPU2 is free running, 1 = CPU2 is stopped with CPU_STOP# 2 1 CPU1 Allow control of CPU1 with CPU_STOP# 0 = CPU1 is free running, 1 = CPU1 is stopped with CPU_STOP# 1 1 CPU0 Allow control of CPU0 with CPU_STOP# 0 = CPU0 is free running, 1 = CPU0 is stopped with CPU_STOP# 0 1 Reserved CLKREQ# drive mode 0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when stopped Reserved Byte 4: Control Register 4 Bit @Pup Name Description 7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ0 control 1 = SRC[T/C]5 stoppable by CLKREQ#0 pin 0 = SRC[T/C]5 free running 6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#0 control 1 = SRC[T/C]4 stoppable by CLKREQ#0 pin 0 = SRC[T/C]4 free running 5 0 SRC[T/C]3 SRC[T/C]3 CLKREQ#0 control 1 = SRC[T/C]3 stoppable by CLKREQ#0 pin 0 = SRC[T/C]3 free running 4 0 SRC[T/C]2 SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running 3 0 SRC[T/C]1 SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running 2 0 SRC[T/C]0 SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running 1 1 Reserved Reserved 0 1 Reserved Reserved Byte 5: Control Register 5 Bit @Pup Name 7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ#1 control 1 = SRC[T/C]5 stoppable by CLKREQ#1 pin 0 = SRC[T/C]5 free running 6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#1 control 1 = SRC[T/C]4 stoppable by CLKREQ#1 pin 0 = SRC[T/C]4 free running Document #: 38-07637 Rev. *B Description Page 6 of 19 [+] Feedback CY28RS400 Byte 5: Control Register 5 (continued) Bit @Pup Name Description 5 0 SRC[T/C]3 SRC[T/C]3 CLKREQ#1 control 1 = SRC[T/C]3 stoppable by CLKREQ#1 pin 0 = SRC[T/C]3 free running 4 0 SRC[T/C]2 SRC[T/C]2 CLKREQ#1 control 1 = SRC[T/C]2 stoppable by CLKREQ#1 pin 0 = SRC[T/C]2 free running 3 0 SRC[T/C]1 SRC[T/C]1 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running 2 0 SRC[T/C]0 SRC[T/C]0 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 6: Control Register 6 Bit @Pup Name Description 7 0 TEST_SEL 6 0 TEST_MODE 5 0 REF 4 0 Reserved Reserved 3 HW 409_410 409_410 reflects the value of the 409_410 pin sampled on power up. 0 = 409_410 was low during VTT_PWRGD# assertion 2 HW FS_C FS_C Reflects the value of the FS_C pin sampled on power up. 0 = FS_C was low during VTT_PWRGD# assertion. 1 HW FS_B FS_B Reflects the value of the FS_B pin sampled on power up. 0 = FS_B was low during VTT_PWRGD# assertion. 0 HW FS_A FS_A Reflects the value of the FS_A pin sampled on power up. 0 = FS_A was low during VTT_PWRGD# assertion. Name Description REF/N or Tri-state Select 1 = REF/N Clock, 0 = Tri-state Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation REF output drive strength. 0 = Low drive, 1 = High drive. Byte 7: Vendor ID Bit @Pup 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 5 0 Revision Code Bit 1 4 1 Revision Code Bit 0 3 1 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Document #: 38-07637 Rev. *B Page 7 of 19 [+] Feedback CY28RS400 Crystal Recommendations The CY28RS400 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS400 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. Table 6. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). The following diagram shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. Figure 1. Crystal Capacitive Clarification Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci2 Ci1 Pin 3 to 6p X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example Document #: 38-07637 Rev. *B Page 8 of 19 [+] Feedback CY28RS400 As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) CL ................................................... Crystal load capacitance CLe .........................................Actual loading seen by crystal using standard value trim capacitors Ce .....................................................External trim capacitors Cs.............................................. Stray capacitance (terraced) Ci ........................................................... Internal capacitance (lead frame, bond wires etc.) PD (Power-down) Clarification The VTT_PWRGD# /PD pin is a dual function pin. During initial power up, the pin functions as VTT_PWRGD#. Once VTT_PWRGD# has been sampled low by the clock chip, the pin assumes PD functionality. The PD pin is an asynchronous active high input used to shut off all clocks cleanly prior to shutting off power to the device. This signal is synchronized internal to the device prior to powering down the clock synthesizer. PD is also an asynchronous input for powering up the system. When PD is asserted high, all clocks need to be driven to a low value and held prior to turning off the VCOs and the crystal oscillator. PD (Power-down) – Assertion When PD is sampled high by two consecutive rising edges of CPUC, all single-ended outputs will be held low on their next high to low transition and differential clocks must held high or Hi-Zd (depending on the state of the control register drive mode bit) on the next diff clock# high to low transition within four clock periods. When the SMBus PD drive mode bit corresponding to the differential (CPU, SRC, and DOT) clock output of interest is programmed to ‘0’, the clock output are held with “Diff clock” pin driven high at 2 x Iref, and “Diff clock#” tristate. If the control register PD drive mode bit corresponding to the output of interest is programmed to “1”, then both the “Diff clock” and the “Diff clock#” are three-state. Note the example below shows CPUT = 133 MHz and PD drive mode = ‘1’ for all differential outputs. This diagram and description is applicable to valid CPU frequencies 100,133,200 and 266MHz. In the event that PD mode is desired as the initial power-on state, PD must be asserted high in less than 10 uS after asserting Vtt_PwrGd#. PD Deassertion The power-up latency is less than 1.8 ms. This is the time from the deassertion of the PD pin or the ramping of the power supply until the time that stable clocks are output from the clock chip. All differential outputs stopped in a three-state condition resulting from power down will be driven high in less than 300 µs of PD deassertion to a voltage greater than 200 mV. After the clock chip’s internal PLL is powered up and locked, all outputs will be enabled within a few clock cycles of each other. Below is an example showing the relationship of clocks coming up. PD CPUT, 133MHz CPUC, 133MHz SRCT 100MHz SRCC 100MHz USB, 48MHz DOT96T DOT96C PCI, 33 MHz REF Figure 3. Power-down Assertion Timing Waveform Document #: 38-07637 Rev. *B Page 9 of 19 [+] Feedback CY28RS400 Tstable 200mV Figure 6. CPU_STP# Deassertion Waveform Document #: 38-07637 Rev. *B Page 10 of 19 [+] Feedback CY28RS400 1.8mS CPU_STOP# PD CPUT(Free Running CPUC(Free Running CPUT(Stoppable) CPUC(Stoppable) Figure 7. CPU_STP#= Driven, CPU_PD = Driven 1.8mS CPU_STOP# PD CPUT(Free Running) CPUC(Free Running) CPUT(Stoppable) CPUC(Stoppable) Figure 8. CPU_STP# = Hi-Z, CPU_PD = Hi-Z CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a de-bounced signal in that it’s state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or de-assertion. (The assertion and de-assertion of this signal is absolutely asynchronous). CLK_REQ[0:1]# De-assertion [Low to High transition] The impact of deasserting the CLKREQ#[1:0] pins is all DIF outputs that are set in the control registers to stoppable via de-assertion of CLKREQ#[1:0] are to be stopped after their next transition. When the control register CLKREQ# drive mode bit is programmed to ‘0’, the final state of all stopped SRC signals is SRCT clock = High and SRCC = Low. There is to be no change to the output drive current values, SRCT will be driven high with a current value equal 6 x Iref,. When the control register CLKREQ# drive mode bit is programmed to ‘1’, the final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven. CLK_REQ[0:1]# Assertion [High to Low transition] All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between two–six SRC clock periods (two clocks are shown) with all SRC outputs resuming simultaneously. If the CLKREQ# drive mode bit is programmed to ‘1’ (three-state), the all stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] assertion to a voltage greater than 200 mV. CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 9. CLK_REQ#[0:1] Assertion/Deassertion Waveform Document #: 38-07637 Rev. *B Page 11 of 19 [+] Feedback CY28RS400 FS_A, FS_B,FS_C VTT_PW RGD# PW RGD_VRM 0.2-0.3mS Delay VDD Clock Gen State 0 Clock State W ait for VTT_PW RGD# State 1 State 2 Off Clock Outputs State 3 On On Off Clock VCO Device is not affected, VTT_PW RGD# is ignored Sample Sels Figure 10. VTT_PWRGD# Timing Diagram S2 S1 Delay >0.25mS VTT_PWRGD# = Low Sample Inputs straps VDD_A = 2.0V Wait for