CY28RS480ZXCT

CY28RS480 Clock Generator for ATI RS480 Chipset • I2C support with readback capabilities Features • Ideal Lexmark Spread Spectrum profile for maximum electromagnetic interference (EMI) reduction • Supports AMD CPU • 200-MHz differential CPU clock pairs • 3.3V power supply • 100-MHz differential SRC clocks • 56-pin SSOP and TSSOP packages • 48-MHz USB clock • 33-MHz PCI clock CPU SRC HTT66 PCI REF USB_48 x2 x8 x1 x1 x3 x1 • 66-MHz HyperTransport clock Block Diagram XIN XOUT CPU_STP# CLKREQ[0:1]# XTAL OSC PLL1 Pin Configuration VDD_REF REF[0:2] PLL Ref Freq VDD_CPU CPUT[0:1], CPUC[0:1], Divider Network VDD_SRC SRCT[0:5],SRCC[0:5] VDD_SRCS SRCST[0:1],SRCSC[0:1] IREF VDD_HTT HTT66 PD VDD_48 MHz PLL2 SDATA SCLK USB_48 I2C Logic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 CY28RS480 VDD_PCI PCI XIN XOUT VDD_48 USB_48 VSS_48 NC SCLK SDATA NC CLKREQ#0 CLKREQ#1 SRCT5 SRCC5 VDD_SRC VSS_SRC SRCT4 SRCC4 SRCT3 SRCC3 VSS_SRC VDD_SRC SRCT2 SRCC2 SRCT1 SRCC1 VSS_SRC SRCST1 SRCSC1 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_REF VSS_REF REF0 REF1 REF2 VDD_PCI PCI0 VSS_PCI VDD_HTT HTT66 VSS_HTT CPUT0 CPUC0 VDD_CPU VSS_CPU CPUT1 CPUC1 VDDA VSSA IREF VSS_SRC1 VDD_SRC1 SRCT0 SRCC0 VDD_SRCS VSS_SRCS SRCST0 SRCSC0 56 SSOP/TSSOP Cypress Semiconductor Corporation Document #: 38-07638 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised February 21, 2005 [+] Feedback CY28RS480 Pin Description Pin No. Name Type Description 41,40,45,44 CPUT/C 50 PCI0 O 33-MHz clock output. 37 IREF I A precision resistor attached to this pin is connected to the internal current reference. 52, 53, 54 REF[2:0] 7 SCLK 8 SDATA 27, 28, 30, 29 SRCST/C[1:0] 12, 13, 16, 17, 18, 19, 22, 23, 24, 25, 34, 33 SRCT/C[5:0] 10,11 CLKREQ#[0:1] 4 USB_48 47 HTT66 O, DIF Differential CPU clock outputs. AMD K8 buffer (200 Mhz). O, SE 14.318-MHz REF clock output. Intel Type-5 buffer. I,PU SMBus-compatible SCLOCK.This pin has an internal pull-up, but is tri-stated in power-down. I/O,PU SMBus-compatible SDATA.This pin has an internal pull-up, but is tri-stated in power-down. O, DIF Differentials Selectable serial reference clock. Intel Type-X buffer. Includes overclock support through SMBUS O, DIF 100-MHz differential serial reference clock. Intel Type-X buffer. I, SE, Output Enable control for SRCT/C. Output enable control required by Minicard PD specification. This pin has an internal pull-down. 0 = Selected SRC outputs are enabled, 1 = Selected SRC outputs are disabled O, SE 48-MHz clock output. Intel Type-3A buffer. O, SE 66-MHz clock output. Intel Type-5 buffer. 3 VDD_48 PWR 3.3V power supply for USB outputs 43 VDD_CPU PWR 3.3V power supply for CPU outputs 51 VDD_PCI PWR 3.3V power supply for PCI outputs 56 VDD_REF PWR 3.3V power supply for REF outputs 48 VDD_HTT PWR 3.3V power supply for Hyper Transport outputs 14, 21 VDD_SRC PWR 3.3V power supply for SRC outputs 35 VDD_SRC1 PWR 3.3V power supply for SRC outputs 32 VDD_SRCS PWR 3.3V power supply for SRCS outputs 39 VDDA PWR 3.3V Analog Power for PLLs 5 VSS_48 GND Ground for USB outputs 42 VSS_CPU GND Ground for CPU outputs 49 VSS_PCI GND Ground for PCI outputs 55 VSS_REF GND Ground for REF outputs 15, 20, 26 VSS_SRC GND Ground for SRC outputs 36 VSS_SRC1 GND Ground for SRC outputs 31 VSS_SRCS GND Ground for SRCS outputs 46 VSS_HTT GND Ground for HyperTransport outputs 38 VSSA GND Analog Ground 1 XIN I 14.318-MHz Crystal Input 2 XOUT O 14.318-MHz Crystal Output 6, 9 NC Document #: 38-07638 Rev. *C No Connects Page 2 of 15 [+] Feedback CY28RS480 Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initializes to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. The interface cannot be used during system operation for power management functions. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 1. The block write and block read protocol is outlined in Table 2 while Table 3 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h). Table 1. Command Code Definition Bit 7 Description 0 = Block read or block write operation, 1 = Byte read or byte write operation (6:5) Chip select address, set to ‘00’ to access device (4:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '00000' Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 8:2 Description Start Write 10 18:11 19 27:20 28 36:29 37 45:38 Bit 1 Slave address – 7 bits 9 Block Read Protocol 8:2 Description Start Slave address – 7 bits 9 Write Acknowledge from slave 10 Acknowledge from slave Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Byte Count – 8 bits 20 Repeat start Acknowledge from slave Data byte 1 – 8 bits Acknowledge from slave Data byte 2 – 8 bits 46 Acknowledge from slave .... Data Byte /Slave Acknowledges .... Data Byte N – 8 bits .... Acknowledge from slave .... Stop 27:21 Slave address – 7 bits 28 Read = 1 29 Acknowledge from slave 37:30 38 46:39 47 55:48 Byte Count from slave – 8 bits Acknowledge Data byte 1 from slave – 8 bits Acknowledge Data byte 2 from slave – 8 bits 56 Acknowledge .... Data bytes from slave / Acknowledge .... Data Byte N from slave – 8 bits .... NOT Acknowledge Table 3. Byte Read and Byte Write Protocol Byte Write Protocol Bit 1 8:2 Description Start Slave address – 7 bits Byte Read Protocol Bit 1 8:2 Description Start Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave Document #: 38-07638 Rev. *C Page 3 of 15 [+] Feedback CY28RS480 Table 3. Byte Read and Byte Write Protocol (continued) Byte Write Protocol Bit 18:11 19 27:20 Byte Read Protocol Description Bit Description Command Code – 8 bits 18:11 Command Code – 8 bits Acknowledge from slave 19 Acknowledge from slave Data byte – 8 bits 20 Repeated start 28 Acknowledge from slave 29 Stop 27:21 Slave address – 7 bits 28 Read 29 Acknowledge from slave 37:30 Data from slave – 8 bits 38 NOT Acknowledge 39 Stop Control Registers Byte 0:Control Register 0 Bit @Pup Name Description 7 1 SRC[T/C]5 SRC[T/C]5 Output Enable 0 = Disable (Hi-Z), 1 = Enable 6 1 SRC[T/C]4 SRC[T/C]4 Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 SRC[T/C]3 SRC[T/C]3 Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 SRC[T/C]2 SRC[T/C]2 Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 SRC[T/C]1 SRC[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 SRC [T/C]0 SRC[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 SRCS[T/C]1 SRCS[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 SRCS[T/C]0 SRCS[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup Name 7 1 REF2 REF2 Output Enable 0 = Disable, 1 = Enable 6 1 REF1 REF1 Output Enable 0 = Disable, 1 = Enable 5 1 REF0 REF0 Output Enable 0 = Disable, 1 = Enable 4 1 PCI0 PCI0 Output Enable 0 = Disable, 1 = Enable 3 1 USB_48 2 1 RESERVED 1 1 CPU[T/C]1 CPU[T/C]1 Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 CPU[T/C]0 CPU[T/C]0 Output Enable 0 = Disable (Hi-Z), 1 = Enable Document #: 38-07638 Rev. *C Description USB_48MHz Output Enable 0 = Disable, 1 = Enable RESERVED Page 4 of 15 [+] Feedback CY28RS480 Byte 2: Control Register 2 Bit @Pup Name Description 7 1 CPUT/C SRCT/C Spread Spectrum Selection ‘0’ = –0.35% ‘1’ = –0.50% 6 1 USB_48 48-MHz Output Drive Strength 0 = 2x, 1 = 1x 5 1 PCI 33-MHz Output Drive Strength 0 = 2x, 1 = 1x 4 0 Reserved Reserved 3 1 Reserved Reserved 2 0 CPU SRC 1 1 Reserved Reserved 0 1 Reserved Reserved CPU/SRC Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 3: Control Register 3 Bit @Pup Name 7 1 CLKREQ# Description 6 0 CPU CPU pd drive mode 0 = CPU clocks driven when power-down, 1 = CPU clocks tri-state 5 1 SRC SRC pd drive mode 0 = SRC clocks driven when power-down, 1 = SRC clocks tri-state 4 0 Reserved Reserved 3 1 Reserved Reserved 2 1 Reserved Reserved 1 1 Reserved Reserved 0 1 HTT66 CLKREQ# drive mode 0 = SRC clocks driven when stopped, 1 = SRC clocks tri-state when stopped HTT66 Output Drive Strength0 = High drive, 1 = Low drive. Byte 4: Control Register 4 Bit @Pup Name 7 0 SRC[T/C]5 SRC[T/C]5 CLKREQ0 control 1 = SRC[T/C]5 stoppable by CLKREQ#0 pin 0 = SRC[T/C]5 free running 6 0 SRC[T/C]4 SRC[T/C]4 CLKREQ#0 control 1 = SRC[T/C]4 stoppable by CLKREQ#0 pin 0 = SRC[T/C]4 free running 5 0 SRC[T/C]3 SRC[T/C]3 CLKREQ#0 control 1 = SRC[T/C]3 stoppable by CLKREQ#0 pin 0 = SRC[T/C]3 free running 4 0 SRC[T/C]2 SRC[T/C]2 CLKREQ#0 control 1 = SRC[T/C]2 stoppable by CLKREQ#0 pin 0 = SRC[T/C]2 free running 3 0 SRC[T/C]1 SRC[T/C]1 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running 2 0 SRC[T/C]0 SRC[T/C]0 CLKREQ#0 control 1 = SRC[T/C]1 stoppable by CLKREQ#0 pin 0 = SRC[T/C]1 free running 1 1 HTT66 Document #: 38-07638 Rev. *C Description HTT66 Output enable 0 = Disabled, 1 = Enabled Page 5 of 15 [+] Feedback CY28RS480 Byte 4: Control Register 4 (continued) Bit @Pup Name Description 0 1 Reserved Reserved Description SRC[T/C]5 CLKREQ#1 control 1 = SRC[T/C]5 stoppable by CLKREQ#1 pin 0 = SRC[T/C]5 free running SRC[T/C]4 CLKREQ#1 control 1 = SRC[T/C]4 stoppable by CLKREQ#1 pin 0 = SRC[T/C]4 free running SRC[T/C]3 CLKREQ#1 control 1 = SRC[T/C]3 stoppable by CLKREQ#1 pin 0 = SRC[T/C]3 free running SRC[T/C]2 CLKREQ#1 control 1 = SRC[T/C]2 stoppable by CLKREQ#1 pin 0 = SRC[T/C]2 free running SRC[T/C]1 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running SRC[T/C]0 CLKREQ#1 control 1 = SRC[T/C]1 stoppable by CLKREQ#1 pin 0 = SRC[T/C]1 free running Reserved Reserved Byte 5: Control Register 5 Bit 7 @Pup 0 Name SRC[T/C]5 6 0 SRC[T/C]4 5 0 SRC[T/C]3 4 0 SRC[T/C]2 3 0 SRC[T/C]1 2 0 SRC[T/C]0 1 0 0 0 Reserved Reserved Byte 6: Control Register 6 Bit @Pup Name Description 7 0 TEST_SEL 6 0 TEST_MODE 5 0 REF 4 1 Reserved Reserved 3 HW Reserved Reserved 2 HW Reserved Reserved 1 HW Reserved Reserved 0 HW Reserved Reserved REF/N or Three-state Select 1 = REF/N Clock, 0 = Three-state Test Clock Mode Entry Control 1 = REF/N or Tri-state mode, 0 = Normal operation REF Output drive strength 0 = Low drive, 1 = High drive Byte 7: Vendor ID Bit @Pup 7 0 Revision Code Bit 3 6 0 Revision Code Bit 2 5 0 Revision Code Bit 1 4 1 Revision Code Bit 0 3 1 Vendor ID Bit 3 2 0 Vendor ID Bit 2 1 0 Vendor ID Bit 1 0 0 Vendor ID Bit 0 Document #: 38-07638 Rev. *C Name Description Page 6 of 15 [+] Feedback CY28RS480 Table 4. Crystal Recommendations Frequency (Fund) Cut Loading Load Cap Drive (max.) Shunt Cap (max.) Motional (max.) Tolerance (max.) Stability (max.) Aging (max.) 14.31818 MHz AT Parallel 0.1 mW 5 pF 0.016 pF 35 ppm 30 ppm 5 ppm 20 pF Crystal Recommendations The CY28RS480 requires a Parallel Resonance Crystal. Substituting a series resonance crystal will cause the CY28RS480 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300-ppm frequency shift between series and parallel crystals due to incorrect loading. series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitive loading on both sides. Clock Chip Ci2 Ci1 Pin 3 to 6p Crystal Loading Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance the crystal will see must be considered to calculate the appropriate capacitive loading (CL). Figure 1 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and should be approximately equal to the load capacitance of the crystal. This is not true. X2 X1 Cs1 Cs2 Trace 2.8pF XTAL Ce1 Ce2 Trim 33pF Figure 2. Crystal Loading Example As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This mean the total capacitance on each side of the crystal must be twice the specified load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) should be calculated to provide equal capacitance loading on both sides. Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Figure 1. Crystal Capacitive Clarification Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Calculating Load Capacitors In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 ) CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) CL ....................................................Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance (lead frame, bond wires etc.) Document #: 38-07638 Rev. *C Page 7 of 15 [+] Feedback CY28RS480 CLK_REQ[0:1]# Description The CLKREQ#[1:0] signals are active low input used for clean stopping and starting selected SRC outputs. The outputs controlled by CLKREQ#[1:0] are determined by the settings in register bytes 4 and 5. The CLKREQ# signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of DIFC to be recognized as a valid assertion or deassertion. (The assertion and deassertion of this signal is absolutely asynchronous.) CLK_REQ[0:1]# Deassertion [Low to High Transition] The impact of deasserting the CLKREQ#[1:0] pins is all DIF outputs that are set in the control registers to stoppable via assertion of CLKREQ#[1:0] are to be stopped after their next transition. When the control register CLKREQ# drive mode bit is programmed to ‘0’, the final state of all stopped SRC signals is SRCT clock = High and SRCC = Low. There is to be no change to the output drive current values, SRCT will be driven high with a current value equal 6 x Iref,. When the control register CLKREQ# drive mode bit is programmed to ‘1’, the final state of all stopped DIF signals is low, both SRCT clock and SRCC clock outputs will not be driven. CLK_REQ[0:1]# Assertion [High to Low Transition] All differential outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the Assertion to active outputs is between 2–6 SRC clock periods (2 clocks are shown) with all SRC outputs resuming simultaneously. If the CLKREQ# drive mode bit is programmed to ‘1’ three-state), the all stopped SRC outputs must be driven high within 10 ns of CLKREQ#[1:0] Assertion to a voltage greater than 200 mV. CLKREQ#X SRCT(free running) SRCC(free running) SRCT(stoppable) SRCT(stoppable) Figure 3. CLK_REQ#[0:1] Assertion/Deassertion Waveform Document #: 38-07638 Rev. *C Page 8 of 15 [+] Feedback CY28RS480 Absolute Maximum Conditions Parameter Description Condition Min. Max. Unit VDD Core Supply Voltage –0.5 4.6 V VDDA Analog Supply Voltage –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD+0.5 VDC TS Temperature, Storage Non-functional –65 +150 °C TA Temperature, Operating Ambient Functional 0 70 °C TJ Temperature, Junction Functional – 150 °C ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 20 °C/W ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 60 °C/W UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level V–0 1 Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. DC Electrical Specifications Parameter Description VDD_REF, 3.3V Operating Voltage VDD_CPU, VDD_PCI, VDD_SRC, VDD_SRC1, VDD_SRCS VDD_48 Condition 3.3V ± 5% VILSMBUS Input Low Voltage SDATA, SCLK VIHSMBUS Input High Voltage SDATA, SCLK VIL Input Low Voltage VDD VIH Input High Voltage IIL Input Leakage Current Except pull-ups or pull-downs 0