CY2907
Single-PLL General Purpose EPROM
Programmable Clock Generator
Features
Benefits
■
Single Phase Locked Loop (PLL) Architecture
■
Generates a custom frequency from an external source
■
EPROM Programmability
■
Easy customization and fast turnaround
■
Factory-Programmable (CY2907) or Field-Programmable
(CY2907F) Device Options
■
Programming support available for all opportunities
Up to Two Configurable Outputs
■
Provides clocking requirements from a single device
■
Low Skew, Low Jitter, High Accuracy Outputs
■
Meets critical industry standard timing requirements
■
Power Management (Power Down, OE)
■
Supports low power applications
■
Frequency Select Option
■
Up to 16 user-selectable frequencies
■
Configurable 5V or 3.3V Operation
■
Supports industry standard design platforms
■
8-pin or 14-pin SOIC Packages
■
Industry standard packaging saves on board space
■
Logic Block Diagram
Cypress Semiconductor Corporation
Document #: 38-07137 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 9, 2009
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CY2907
Pin Configurations
Figure 1. 14-Pin SOIC and 8-Pin SOIC (Top View)
S1
S2
S3
VSS
VSS
PD
XTALIN
14
13
12
11
10
9
8
1
2
3
4
5
6
7
S0
REFCLK
VDD
CLKA
OEA
OER
XTALOUT
S0
VSS
XTALIN
XTALOUT
1
2
3
4
8
7
6
5
REFCLK
VDD
CLKA
S1
Pin Description
Name
Pin Number
Description
14-Pin SOIC
8-Pin SOIC
S1
1
5
Frequency Select (CLKA) (Internal pull up resistor to VDD)
S2
2
NA
Frequency Select (CLKA) (Internal pull up resistor to VDD)
S3
3
NA
Frequency Select (CLKA) (Internal pull up resistor to VDD)
VSS
4
2
Ground
VSS
5
NA
Ground
PD
6
NA
Power Down (Active LOW) (Internal pull up resistor to VDD)
XTALIN[1]
7
3
Reference Crystal Input
XTALOUT[1, 2]
8
4
Reference Crystal Feedback
OER
9
NA
REFCLK Output Enable (Active HIGH) (Internal pull up resistor to VDD)
OEA
10
NA
CLKA Output Enable (Active HIGH) (Internal pull up resistor to VDD)
CLKA
11
6
Clock Output
VDD
12
7
Voltage Supply
REFCLK
13
8
Reference Clock Output (Default, can be driven by PLL if desired)
S0
14
1
Frequency Select (CLKA) (Internal pull up resistor to VDD)
Notes
1. For best accuracy, use a parallel resonant crystal, CLOAD ≈ 17 pF.
2. Float XTALOUT pin if XTALIN is driven by reference clock (as opposed to crystal).
Document #: 38-07137 Rev. *B
Page 2 of 9
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CY2907
Functional Description
The CY2907 is a general purpose clock generator designed for
use in a wide variety of applications—from graphics to PC
peripherals to disk drives. It generates selectable system clock
frequencies from a single reference input (crystal or reference
clock). The CY2907 is configured with an EPROM array, similar
to the other devices in the Cypress EPROM Programmable
Clock family, making it easy to customize for any application.
Furthermore, the CY2907 is compatible with all industry standard
9107 and 9108 clock synthesizers.
Device Programming
Two versions of the CY2907 are available - Field Programmable
and Factory Programmable. Field programmable devices must
be programmed before being installed in an application. They
are one-time-programmable (OTP). Customers can program
small quantities in-house using the Cypress CY3670
programmer. Production quantities are available through
Cypress’s value-added distribution partners, or by using third
party programmers from BP Microsystems, Hi-Lo Systems, and
others.
Note the output frequency ranges in this data sheet when specifying them in CyberClocks to make sure that you stay within the
limits. After a configuration is established, you can print the
configuration and save programming files in ENT and JED
formats.
CyberClocks runs on PCs running the Windows™ operating
system, and is available for free download on the Cypress
Semiconductor website at www.cypress.com.
Within the CyberClocks application, the CY2907 is found in the
CyClocks™ section. Note that the standalone CyberClocks
software should not be confused with the CyberClocks Online
software, which is a web-based application that is used to
configure other programmable clock devices.
Cypress CY3670 Programming Kit
Cypress’s CY3670 is a portable programmer that connects to a
PC serial port and enables users of CyClocks software to quickly
and easily program any of the CY2291F, CY2292F, CY2071AF,
and CY2907F devices. An adapter is also required and is
ordered separately. The CY3097 is the adapter for the
CY2907F8. For the CY2907F14, order adapter CY3098.
For high volume orders, devices can be factory programmed by
Cypress. All requests must be submitted to the local Cypress
Field Application Engineer (FAE) or sales representative. After
the request is processed, you receive a new part number,
samples, and a data sheet with the programmed values. This
part number is used for additional sample requests and
production orders.
Maximum Ratings
CyberClocks™ Software
Storage Temperature (Non-Condensing).... –65°C to +150°C
CyberClocks is an easy-to-use software application that enables
the user to configure any one of the EPROM Programmable
Clocks offered by Cypress. You may specify the input frequency,
PLL and output frequencies, and different functional options.
Junction Temperature ............................................... +150°C
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Supply Voltage.................................................. –0.5 to +7.0V
Input Voltage............................................ –0.5V to VDD+0.5V
Max Soldering Temperature (10 sec) ....................... +260°C
Static Discharge Voltage............................................ >2000V
(per MIL-STD-883, Method 3015)
Operating Conditions[3]
Parameter
VDD
Description
Min
Max
Unit
Supply Voltage, 5V Operation
4.5
5.5
V
Supply Voltage, 3.3V Operation
3.0
3.6
V
0
70
°C
15
pF
10.0
25.0
MHz
1.0
30.0
MHz
TA
Commercial Operating Temperature, Ambient
CL
Max. Capacitive Load
fREF
External Reference Crystal
External Reference Clock
Document #: 38-07137 Rev. *B
[4, 5]
Page 3 of 9
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CY2907
Electrical Characteristics at 5.0V Commercial VDD = 4.5V to 5.5V, TA = 0°C to +70°C
Parameter
Description
Test Conditions
Min
VIH
High-level Input Voltage
Except Crystal Inputs
VIL
Low-level Input Voltage
Except Crystal Inputs
VOH[4]
VOL[4]
IOH[4]
IOL[4]
High-level Output Voltage
Low-level Output Voltage
VDD = VDD Min. IOH = –30 mA
VDD = VDD Min. IOL = 10 mA
Output High Current
VOH = 2.0V
Output Low Current
VOL = 0.8V
22
IIH
Input High Current
VIH = VDD
–2
IIL
Input Low Current
VIL = 0V
IDD[5]
Power Supply Current
IDD
Power Supply Current
IDD
RPU[4]
Max
2.0
V
0.8
CLKA
2.4
CLKA
Unit
V
V
0.4
V
–35
mA
mA
2
μA
20
μA
PD HIGH, CLKA = 50 MHz
42
mA
PD LOW, Logic Inputs LOW
100
μA
Power Supply Current
PD LOW, Logic Inputs HIGH
40
μA
Pull Up Resistor
VIN = VDD – 1.0 V
700
kΩ
Max
Unit
Electrical Characteristics at 3.3V Commercial VDD = 3.0V to 3.6V, TA = 0°C to +70°C
Parameter
Description
Test Conditions
Min
VIH
High-level Input Voltage
Except Crystal Inputs
0.7*VDD
VIL
Low-level Input Voltage
Except Crystal Inputs
VOH[4]
High-level Output Voltage
CLKA, IOH = –5 mA
VOL[4]
IOH[4]
IOL[4]
Low-level Output Voltage
CLKA, IOL = 6 mA
Output High Current
VOH = 0.7*VDD
Output Low Current
VOL = 0.2*VDD
15
IIH
Input High Current
VIH = VDD
–2
IIL
Input Low Current
IDD[5]
V
0.2*VDD
0.85*VDD
V
V
0.1*VDD
V
–10
mA
mA
2
μA
VIL = 0V
10
μA
Power Supply Current
PD HIGH, CLKA = 50 MHz
40
mA
IDD
Power Supply Current
PD LOW, Logic Inputs LOW
40
μA
IDD
Power Supply Current
PD LOW, Logic Inputs HIGH
12
μA
RPU[4]
Pull Up Resistor
VIN = VDD – 0.5V
900
kΩ
Notes
3. Electrical parameters are guaranteed with these operating conditions.
4. Guaranteed by design, not 100% tested in production.
5. Load = max. typical configuration, fREF = 14.318 MHz. Specific configurations may vary. A close approximation of IDD can be derived by the following formula:
IDD (mA) = VDD * (6.25 + (0.055*FREF) + (0.0017*CLOAD*(FCLKA + REFCLK))). CLOAD is specified in pF and F is specified in MHz.
Document #: 38-07137 Rev. *B
Page 4 of 9
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CY2907
Switching Characteristics at 5.0V Commercial[4]
Parameter
Output[6]
Description
Test Conditions
Min
Max
Unit
tR
CLKA
Output Rise Time 0.8V to 2.0V
15-pF Load
1.40
ns
tF
CLKA
Output Fall Time 2.0V to 0.8V
15-pF Load
1.00
ns
tR
CLKA
Output Rise Time 20% to 80%
15-pF Load
3.5
ns
tF
CLKA
Output Fall Time 80% to 20%
15-pF Load
2.5
ns
tD
CLKA
Duty Cycle
15-pF Load at 1.4V
45.0
55.0
%
FI
XTALIN
Input Frequency
Crystal Oscillator
10
25
MHz
FI
XTALIN
Input Frequency
External Input Clock[7]
1
30
MHz
FO
CLKA
Output Frequency
CY2907, 15-pF Load
0.5
130.0
MHz
CY2907F, 15-pF Load
0.5
100.0
MHz
tJIS
CLKA
Jitter (One Sigma)
20 MHz to 130 MHz
150
ps
tJIS
CLKA
Jitter (One Sigma)
14 MHz to 20 MHz
200
ps
tJIS
CLKA
Jitter (One Sigma)
Less than 14 MHz
1
%
tJAB
CLKA
Jitter (Absolute)
20 MHz to 130 MHz
–250
+ 250
ps
tJAB
CLKA
Jitter (Absolute)
14 MHz to 20 MHz
–500
+ 500
ps
tJAB
CLKA
Jitter (Absolute)
Less than 14 MHz
3
%
18
ms
13
ms
Max
Unit
tPU
tFT
Power Up Time
CLKA
Transition Time
8 MHz to 66.6 MHz
Switching Characteristics at 3.3V Commercial[4]
Parameter
Output[6]
Description
Test Conditions
Min
tR
CLKA
Output Rise Time 20% to 80%
15-pF Load
3.5
ns
tF
CLKA
Output Fall Time 80% to 20%
15-pF Load
2.5
ns
tD
CLKA
Duty Cycle
15-pF Load at 1.4V
40.0
53.0
%
FI
XTALIN
Input Frequency
Crystal Oscillator
10
25
MHz
FI
XTALIN
Input Frequency
External Input Clock[7]
1
30
MHz
FO
CLKA
Output Frequency
CY2907, 15-pF Load
0.5
100.0
MHz
CY2907F, 15-pF Load
0.5
80.0
MHz
tJIS
CLKA
Jitter (One Sigma)
25 MHz to 100 MHz
150
ps
tJIS
CLKA
Jitter (One Sigma)
14 MHz to 25 MHz
200
ps
tJIS
CLKA
Jitter (One Sigma)
Less than 14 MHz
1
%
tJAB
CLKA
Jitter (Absolute)
25 MHz to 120 MHz
–250
+250
ps
tJAB
CLKA
Jitter (Absolute)
14 MHz to 25 MHz
–500
+500
ps
tJAB
CLKA
Jitter (Absolute)
Less than 14 MHz
3
%
18
ms
13
ms
Power Up Time
tPU
tFT
CLKA
Transition Time
8 MHz to 66.6 MHz
Notes
6. REFCLK output can also be configured to be driven by the PLL. In that case these characteristics are also valid.
7. Refer to the application note Crystal Oscillator Topics when using an external reference clock as an input frequency source.
:
Document #: 38-07137 Rev. *B
Page 5 of 9
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CY2907
Switching Waveforms
Figure 2. Frequency Select Change (Transition Time)
OLD SELECT
SELECT
NEW SELECT STABLE
Fold
Fnew
tFT
CLKA
Figure 3. Duty Cycle Timing
tD = t2 ÷ t1
t1
t2
CLKA
1.4V
Figure 4. All Outputs Rise/Fall Time
CLKA
80%
20%
tR
tF
Test Circuit
Figure 5. Test Circuit
VDD
VDD
CLKA
CLOAD
0.1 μF
OUTPUTS
REFCLK
CLOAD
Note: All capacitors should be placed as close to each pin as possible.
Document #: 38-07137 Rev. *B
Page 6 of 9
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CY2907
Ordering Information
Ordering Code
Package Type
Operating Range
CY2907SL-xxx[8]
8-pin or 14-pin SOIC
3.3V, Commercial, Factory Programmable
CY2907SL-xxxT[8]
8-pin or 14-pin SOIC - Tape and Reel
3.3V, Commercial, Factory Programmable
CY2907F8[8]
8-pin SOIC
5.0V/3.3V, Commercial, Field Programmable
CY2907F14
14-pin SOIC
5.0V/3.3V, Commercial, Field Programmable
CY3670
Cypress FTG Programmer
Custom Programming for Field Programmable Clocks
8-pin SOIC
5.0V/3.3V, Commercial, Field Programmable
CY2907FX8T
8-pin SOIC - Tape and Reel
5.0V/3.3V, Commercial, Field Programmable
CY2907FX14[8]
14-pin SOIC
5.0V/3.3V, Commercial, Field Programmable
CY2907FX14T[8]
14-pin SOIC - Tape and Reel
5.0V/3.3V, Commercial, Field Programmable
[8]
Pb-free
CY2907FX8[8]
[8]
Package Characteristics
θJA (C/W)
θJC (C/W)
Transistor Count
8-pin SOIC
170
35
5436
14-pin SOIC
140
31
5436
Package
Package Diagrams
Figure 6. 8-Pin (150-Mil) SOIC
8 Lead (150 Mil) SOIC - S08
PIN 1 ID
4
1
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.150[3.810]
0.157[3.987]
3. REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
4. PACKAGE WEIGHT 0.07gms
PART #
S08.15 STANDARD PKG.
5
SZ08.15 LEAD FREE PKG.
8
0.189[4.800]
0.196[4.978]
0.010[0.254]
0.016[0.406]
SEATING PLANE
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
51-85066-*C
Note
8. Not for new designs. New designs should use a device other than the CY2907.
Document #: 38-07137 Rev. *B
Page 7 of 9
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CY2907
Figure 7. 14-Pin (150-Mil) SOIC
PIN 1 ID
7
1
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.150[3.810]
0.157[3.987]
REFERENCE JEDEC MS-012
0.230[5.842]
0.244[6.197]
PART #
S14.15 STANDARD PKG.
SZ14.15 LEAD FREE PKG.
8
14
0.010[0.254]
0.016[0.406]
SEATING PLANE
0.337[8.559]
0.344[8.7376]
X 45°
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.050[1.270]
BSC
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
Document #: 38-07137 Rev. *B
0°~8°
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
51-85067-*B
Page 8 of 9
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CY2907
Document History Page
Document Title: CY2907 Single-PLL General Purpose EPROM Programmable Clock Generator
Document Number: 38-07137
REV.
ECN NO.
Submission
Date
Orig. of
Change
**
110246
12/18/2001
SZV
*A
1088524
See ECN
KVM/
Added Pb-free for CY2907F8 and CY2907F14 field programmable devices
KKVTMP Updated and added to text on page 2
Applied new template
*B
2715646
6/10/2009
KVM/AESA Removed obsolete part numbers from the ordering information table:
CY2907SC-xxx, CY2907SC-xxxT, CY2907SI-xxx, CY2907SI-xxxT,
CY2907F8T, CY2907F8I, CY2907F8IT, CY2907F14T, CY2907F14I and
CY2907F14IT
Added note: “Not for new designs”
Removed industrial temperature references: page 1 features list, TA spec, DC
and AC electrical tables
Removed Selector Guide table from page 1
Description of Change
Change from Spec number: 38-00505 to 38-07137
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© Cypress Semiconductor Corporation, 2007-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 38-07137 Rev. *B
Revised June 9, 2009
All products and company names mentioned in this document may be the trademarks of their respective holders.
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