CY29350AI

CY29350 2.5V or 3.3V, 200-MHz, 9-Output Clock Driver Features • • • • • • • • • • • • • • Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs ±2.5% max Output duty cycle variation Nine Clock outputs: Drive up to 18 clock lines Two reference clock inputs: Xtal or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread Aware™ Output enable/disable Pin-compatible with MPC9350 Industrial temperature range: –40°C to +85°C 32-pin 1.0mm TQFP package Functional Description The CY29350 is a low-voltage high-performance 200-MHz PLL-based clock driver designed for high speed clock distribution applications. The CY29350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see . These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Block Diagram Pin Configuration SELA PLL_EN REF_SEL PLL_EN TCLK VSS XIN XOUT 32 31 30 29 28 27 26 25 OSC Phase Detector VCO 200 500MHz ÷2 / ÷4 QA AVDD FB _S E L S E LA S E LB SE LC SE LD A V SS XO U T 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 QC0 VD D Q C QC1 VS S QD0 VD D Q D QD1 VS S LPF ÷16 / ÷32 FB_SEL SELB SELC ÷4 / ÷8 QB C Y 29350 ÷4 / ÷8 QC0 QC1 9 10 11 12 13 14 QD3 15 VDDQD OE# QD4 VSS ÷4 / ÷8 SELD QD0 QD1 QD2 QD3 QD4 OE# Cypress Semiconductor Corporation Document #: 38-07474 Rev. *A • 3901 North First Street • San Jose, CA 95134 VDD QD2 XIN 16 VSS QA QB REF_SEL TCLK VDDQB • 408-943-2600 Revised July 26, 2004 CY29350 Pin Definitions[1] Pin 8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 10 31 32 3, 4, 5, 6 27 23 15, 19 1 11 7 13, 17, 21, 25, 29 XIN TCLK QA QB QC(1:0) QD(4:0) FB_SEL OE# PLL_EN REF_SEL SEL(A:D) VDDQB VDDQC VDDQD AVDD VDD AVSS VSS Name XOUT I/O O I I, PD O O O O I, PD I, PD I, PU I, PD I, PD Supply Supply Supply Supply Supply Supply Supply Type Analog Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground Description Oscillator Output. Connect to a crystal. Oscillator Input. Connect to a crystal. LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Clock output bank D Internal Feedback Select Input. See Table 1. Output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. Frequency select input, Bank (A:D). See Table 2. 2.5V or 3.3V Power supply for bank B output clock[2,3] 2.5V or 3.3V Power supply for bank C output clocks[2,3] 2.5V or 3.3V Power supply for bank D output clocks[2,3] 2.5V or 3.3V Power supply for PLL[2,3] 2.5V or 3.3V Power supply for core, inputs, and bank A output clock[2,3] Analog ground Common ground Table 1. Frequency Table FB_SEL 0 1 Table 2. Function Table Control REF_SEL PLL_EN OE# FB_SEL SELA SELB SELC SELD Default 0 1 0 0 0 0 0 0 0 Xtal Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs enabled Feedback divider ÷ 32 ÷ 2 (Bank A) ÷ 4 (Bank B) ÷ 4 (Bank C) ÷ 4 (Bank D) ÷ 8 (Bank B) ÷ 8 (Bank C) ÷ 8 (Bank D) 1 TCLK PLL enabled. The VCO output connects to the output dividers Outputs disabled (three-state) Feedback divider ÷ 16 ÷ 4 (Bank A ) Feedback Divider ÷32 ÷16 VCO Input Clock * 32 Input Clock * 16 Input Frequency Range (AVDD = 3.3V) 6.25 MHz to 15.625 MHz 12.5 MHz to 31.25 MHz Input Frequency Range (AVDD = 2.5V) 6.25 MHz to 11.875 MHz 12.5 MHz to 23.75 MHz Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1µF bypass capacitor should be placed as close as possible to each positive power pin ( 100 MHz 0.6V to 1.8V Condition Min. 200 12.5 6.25 0 10 25 – 100 50 25 47.5 45 0.1 – – – – – – – – – – Typ. – – – – – – – – – – – – – – – – 0.7 - 0.9 0.6 - 0.8 – – – – – Max. 380 23.75 11.87 200 23.75 75 1.0 190 95 47.5 52.5 55 1.0 150 10 10 – – 150 250 100 175 1 ms ps ps ns ps ns ns MHz % MHz % ns MHz Unit MHz MHz AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C) [6] Parameter fVCO fin Description VCO Frequency Input Frequency Condition ÷16 Feedback ÷32 Feedback Bypass mode (PLL_EN = 0) Min. 200 12.5 6.25 0 10 25 Typ. – – – – – – – – – – – – – – – – – Max. 500 31.25 15.625 200 25 75 1.0 200 125 62.5 52.5 55 1.0 150 350 10 10 Unit MHz MHz fXTAL frefDC tr , tf fMAX Crystal Oscillator Frequency Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency 0.8V to 2.0V ÷2 Output ÷4 Output ÷8 Output MHz % ns MHz – 100 50 25 47.5 45 0.1 – – – – DC tr , tf tsk(O) tsk(B) tPLZ, HZ tPZL, ZH Output Duty Cycle Output Rise/Fall times Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time fMAX < 100 MHz fMAX > 100 MHz 0.8V to 2.4V Banks at same voltage Banks at different voltages % ns ps ps ns ns Note: 6. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested. Document #: 38-07474 Rev. *A Page 4 of 7 CY29350 AC Electrical Specifications (VDD = 3.3V ± 5%, TA = –40°C to +85°C)(continued)[6] Parameter BW tJIT(CC) tJIT(PER) tLOCK Description PLL Closed Loop Bandwidth (–3dB) Cycle-to-Cycle Jitter Period Jitter Maximum PLL Lock Time Zo = 50 ohm R T = 5 0 ohm Condition ÷16 Feedback ÷32 Feedback Same frequency Multiple frequencies Same frequency Multiple frequencies Min. – – – – – – – Zo = 50 ohm Typ. 0.7 – 0.9 0.6 – 0.8 – – – – – Max. – – 150 250 100 150 1 Unit MHz ps ps ms Pulse Generator Z = 50 ohm R T = 5 0 ohm VTT VTT Figure 1. AC Test Reference for VDD = 3.3V / 2.5V VDD tP T0 VDD/2 GND DC = tP / T0 x 100% Figure 2. Output Duty Cycle (DC) VDD VDD/2 GND VDD VDD/2 tSK(O) GND Figure 3. Output-to-Output Skew , tsk(O) Table 3. Suggested Oscillator Crystal Parameters Characteristic Frequency Tolerance Frequency Temperature Stability Aging Load Capacitance Effective Series Resistance Symbol TC TS TA CL RESR (TA –10 +60C) First three years @ 25C Crystal’s rated load Conditions Min – – – – – Typ – – – 20 40 Max ±100 ±00 5 – 80 Units PPM PPM PPM/yr pF Ω Ordering Information Part Number CY29350AI CY29350AIT 32-pin TQFP 32-pin TQFP – Tape and Reel Package Type Product Flow Industrial, –40°C to +85°C Industrial, –40°C to 85°C Document #: 38-07474 Rev. *A Page 5 of 7 CY29350 Package Drawing and Dimension 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0 mm A32 51-85063-*B Spread Aware is a trademark of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07474 Rev. *A Page 6 of 7 © Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY29350 Document History Page Document Title:CY29350 2.5V or 3.3V, 200-MHz, 9-Output Clock Driver Document Number: 38-07474 Rev. ** *A ECN No. 128104 245393 Issue Date 07/07/03 See ECN Orig. of Change RGL RGL New Data Sheet Re-worded Select Function Descriptions in table 2. Description of Change Document #: 38-07474 Rev. *A Page 7 of 7