CY29350AXIT

CY29350 2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver 2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Functional Description The CY29350 is a low-voltage high-performance 200-MHz PLL-based clock driver designed for high speed clock distribution applications. The CY29350 features Xtal and LVCMOS reference clock inputs and provides nine outputs partitioned in four banks of 1, 1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4 while the other banks divide by 4 or 8 per SEL(A:D) settings, see . These dividers allow output to input ratios of 16:1, 8:1, 4:1, and 2:1. Each LVCMOS compatible output can drive 50  series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:18. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 200 MHz. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Table 1. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Output frequency range: 25 MHz to 200 MHz Input frequency range: 6.25 MHz to 31.25 MHz 2.5 V or 3.3 V operation Split 2.5 V/3.3 V outputs ±2.5% max Output duty cycle variation Nine Clock outputs: Drive up to 18 clock lines Two reference clock inputs: Xtal or LVCMOS 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread Aware™ Output enable/disable Pin-compatible with MPC9350 Industrial temperature range: –40 °C to +85 °C 32-pin 1.0 mm TQFP package Block Diagram SELA PLL_EN REF_SEL TCLK XIN XOUT OSC Phase Detector VCO 200 500MHz  QA LPF  FB_SEL SELB SELC  QB  QC0 QC1  SELD QD0 QD1 QD2 QD3 QD4 OE# Cypress Semiconductor Corporation Document Number: 38-07474 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 12, 2011 [+] Feedback CY29350 Contents Pin Configuration ............................................................. 3 Pin Definitions .................................................................. 4 Absolute Maximum Conditions ....................................... 5 DC Electrical Specifications ............................................ 6 DC Electrical Specifications ............................................ 6 AC Electrical Specifications ............................................ 7 AC Electrical Specifications ............................................ 8 Ordering Information ...................................................... 10 Ordering Code Definitions ......................................... 10 Package Drawing and Dimension ................................. 10 Acronyms ........................................................................ 11 Document Conventions ................................................. 11 Units of Measure ....................................................... 11 Document History Page ................................................. 12 Sales, Solutions, and Legal Information ...................... 13 Worldwide Sales and Design Support ....................... 13 Products .................................................................... 13 PSoC Solutions ......................................................... 13 Document Number: 38-07474 Rev. *C Page 2 of 13 [+] Feedback CY29350 Pin Configuration REF_SEL PLL_EN TCLK VSS QA VDDQB QB VSS 32 31 30 29 28 27 26 25 AVDD FB_SEL SELA SELB SELC SELD AVSS XOUT 1 2 3 4 5 6 7 8 CY29350 24 23 22 21 20 19 18 17 QC0 VDDQC QC1 VSS QD0 VDDQD QD1 VSS Document Number: 38-07474 Rev. *C XIN OE# VDD QD4 VSS QD3 VDDQD QD2 9 10 11 12 13 14 15 16 Page 3 of 13 [+] Feedback CY29350 Pin Definitions[1] Pin 8 9 30 28 26 22, 24 12, 14, 16, 18, 20 2 10 31 32 3, 4, 5, 6 27 23 15, 19 1 11 7 13, 17, 21, 25, 29 XIN TCLK QA QB QC(1:0) QD(4:0) FB_SEL OE# PLL_EN REF_SEL SEL(A:D) VDDQB VDDQC VDDQD AVDD VDD AVSS VSS Name XOUT I/O O I I, PD O O O O I, PD I, PD I, PU I, PD I, PD Supply Supply Supply Supply Supply Supply Supply Type Analog Analog LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD Ground Ground Description Oscillator Output. Connect to a crystal. Oscillator Input. Connect to a crystal. LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Clock output bank D Internal Feedback Select Input. See Table 1. Output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. Frequency select input, Bank (A:D). See Table 2. 2.5 V or 3.3 V Power supply for bank B output clock[2, 3] 2.5 V or 3.3 V Power supply for bank C output clocks[2, 3] 2.5 V or 3.3 V Power supply for bank D output clocks[2, 3] 2.5 V or 3.3 V Power supply for PLL[2, 3] 2.5 V or 3.3 V Power supply for core, inputs, and bank A output clock[2, 3] Analog ground Common ground Table 1. Frequency Table FB_SEL 0 1 Table 2. Function Table Control REF_SEL PLL_EN OE# FB_SEL SELA SELB SELC SELD Default 0 1 0 0 0 0 0 0 0 Xtal Bypass mode, PLL disabled. The input clock connects to the output dividers Outputs enabled Feedback divider  32  2 (Bank A)  4 (Bank B)  4 (Bank C)  4 (Bank D)  8 (Bank B)  8 (Bank C)  8 (Bank D) 1 TCLK PLL enabled. The VCO output connects to the output dividers Outputs disabled (three-state) Feedback divider  16  4 (Bank A ) Feedback Divider 32 16 VCO Input Clock * 32 Input Clock * 16 Input Frequency Range (AVDD = 3.3 V) 6.25 MHz to 15.625 MHz 12.5 MHz to 31.25 MHz Input Frequency Range (AVDD = 2.5 V) 6.25 MHz to 11.875 MHz 12.5 MHz to 23.75 MHz Notes 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1F bypass capacitor should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their high frequency filtering characteristics will be cancelled by the lead inductance of the traces. 3. AVDD and VDD pins must be connected to a power supply level that is at least equal or higher than that of VDDQB, VDDQC, and VDDQD output power supply pins. Document Number: 38-07474 Rev. *C Page 4 of 13 [+] Feedback CY29350 Absolute Maximum Conditions Parameter VDD VDD VIN VOUT VTT LU RPS TS TA TJ ØJC ØJA ESDH FIT Description DC Supply Voltage DC Operating Voltage DC Input Voltage DC Output Voltage Output termination Voltage Latch Up Immunity Power Supply Ripple Temperature, Storage Temperature, Operating Ambient Temperature, Junction Dissipation, Junction to Case Dissipation, Junction to Ambient ESD Protection (Human Body Model) Failure in Time Condition Functional Relative to VSS Relative to VSS Functional Ripple Frequency < 100 kHz Non-functional Functional Functional Functional Functional Manufacturing test Min –0.3 2.375 –0.3 –0.3 – 200 – –65 –40 – – – 2000 Max 5.5 3.465 VDD + 0.3 VDD + 0.3 VDD  2 – 150 +150 +85 +150 42 105 – 10 Unit V V V V V mA mVp-p °C °C °C °C/W °C/W Volts ppm Document Number: 38-07474 Rev. *C Page 5 of 13 [+] Feedback CY29350 DC Electrical Specifications (VDD = 2.5 V ± 5%, TA = –40 °C to +85 °C) Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Output Voltage, Low[4] Output Voltage, High[4] Input Current, Low[5] Input Current, High[5] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance Condition LVCMOS LVCMOS IOL = 15mA IOH = –15mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz Min – 1.7 – 1.8 – – – – – – – 14 Typ – – – – – – 5 – 180 210 4 18 Max 0.7 VDD + 0.3 0.6 – –100 100 10 7 – – – 22 Unit V V V V A A mA mA mA pF  DC Electrical Specifications (VDD = 3.3 V ± 5%, TA = –40 °C to +85 °C) Parameter VIL VIH VOL VOH IIL IIH IDDA IDDQ IDD CIN ZOUT Description Input Voltage, Low Input Voltage, High Output Voltage, Low[4] Output Voltage, High[4] Input Current, Low[5] Input Current, High[5] PLL Supply Current Quiescent Supply Current Dynamic Supply Current Input Pin Capacitance Output Impedance Condition LVCMOS LVCMOS IOL = 24 mA IOL = 12 mA IOH = –24 mA VIL = VSS VIL = VDD AVDD only All VDD pins except AVDD Outputs loaded @ 100 MHz Outputs loaded @ 200 MHz Min – 2.0 – – 2.4 –– – – – – – – 12 Typ – – – – – – – 5 – 270 300 4 15 Max 0.8 VDD + 0.3 0.55 0.30 – –100 100 10 7 – – – 18 Unit V V V V A A mA mA mA pF  Notes 4. Driving one 50  parallel terminated transmission line to a termination voltage of VTT. Alternatively, each output drives up to two 50  series terminated transmission lines. 5. Inputs have pull-up or pull-down resistors that affect the input current. Document Number: 38-07474 Rev. *C Page 6 of 13 [+] Feedback CY29350 AC Electrical Specifications (VDD = 2.5 V ± 5%, TA = –40 °C to +85 °C) [6] Parameter fVCO fin Description VCO Frequency Input Frequency 16 Feedback 32 Feedback Bypass mode (PLL_EN = 0) fXTAL frefDC tr , tf fMAX Crystal Oscillator Frequency Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency 0.7 V to 1.7 V 2 Output 4 Output 8 Output DC tr, tf tsk(O) tPLZ, HZ tPZL, ZH BW tJIT(CC) tJIT(PER) tLOCK Output Duty Cycle Output Rise/Fall times Output-to-Output Skew Output Disable Time Output Enable Time PLL Closed Loop Bandwidth (–3 dB) 16 Feedback 32 Feedback Cycle-to-Cycle Jitter Period Jitter Maximum PLL Lock Time Same frequency Multiple frequencies Same frequency Multiple frequencies fMAX < 100 MHz fMAX > 100 MHz 0.6V to 1.8V Condition Min 200 12.5 6.25 0 10 25 – 100 50 25 47.5 45 0.1 – – – – – – – – – – Typ – – – – – – – – – – – – – – – – 0.7–0.9 0.6–0.8 – – – – – Max 380 23.75 11.87 200 23.75 75 1.0 190 95 47.5 52.5 55 1.0 150 10 10 – – 150 250 100 175 1 ms ps ps ns ps ns ns MHz % MHz % ns MHz Unit MHz MHz Note 6. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. Document Number: 38-07474 Rev. *C Page 7 of 13 [+] Feedback CY29350 AC Electrical Specifications (VDD = 3.3 V ± 5%, TA = –40 °C to +85 °C) [7] Parameter fVCO fin Description VCO Frequency Input Frequency Condition 16 Feedback 32 Feedback Bypass mode (PLL_EN = 0) Min 200 12.5 6.25 0 10 25 Typ – – – – – – – – – – – – – – – – – Max 500 31.25 15.625 200 25 75 1.0 200 125 62.5 52.5 55 1.0 150 350 10 10 Unit MHz MHz fXTAL frefDC tr, tf fMAX Crystal Oscillator Frequency Input Duty Cycle TCLK Input Rise/FallTime Maximum Output Frequency 0.8 V to 2.0 V 2 Output 4 Output 8 Output MHz % ns MHz – 100 50 25 47.5 45 0.1 – – – – DC tr , tf tsk(O) tsk(B) tPLZ, HZ tPZL, ZH Output Duty Cycle Output Rise/Fall times Output-to-Output Skew Bank-to-Bank Skew Output Disable Time Output Enable Time fMAX < 100 MHz fMAX > 100 MHz 0.8 V to 2.4 V Banks at same voltage Banks at different voltages % ns ps ps ns ns BW tJIT(CC) tJIT(PER) tLOCK PLL Closed Loop Bandwidth (–3 dB) 16 Feedback 32 Feedback Cycle-to-Cycle Jitter Period Jitter Maximum PLL Lock Time Same frequency Multiple frequencies Same frequency Multiple frequencies – – – – – – – 0.7–0.9 0.6–0.8 – – – – – – – 150 250 100 150 1 MHz ps ps ms Note 7. AC characteristics apply for parallel output termination of 50 to VTT. Parameters are guaranteed by characterization and are not 100% tested. Document Number: 38-07474 Rev. *C Page 8 of 13 [+] Feedback CY29350 Figure 1. AC Test Reference for VDD = 3.3 V / 2.5 V Pulse Generator Z = 50 ohm Zo = 50 ohm R T = 5 0 ohm Zo = 50 ohm R T = 5 0 ohm VTT VTT Figure 2. Output Duty Cycle (DC) VDD tP T0 VDD/2 GND DC = tP / T0 x 100% Figure 3. Output-to-Output Skew , tsk(O) VDD VDD/2 GND VDD VDD/2 tSK(O) GND Table 3. Suggested Oscillator Crystal Parameters Characteristic Frequency Tolerance Frequency Temperature Stability Aging Load Capacitance Effective Series Resistance Symbol TC TS TA CL RESR (TA –10 +60 °C) First three years @ 25 °C Crystal’s rated load Conditions Min – – – – – Typ – – – 20 40 Max ±100 ±00 5 – 80 Units ppm ppm ppm/yr pF  Document Number: 38-07474 Rev. *C Page 9 of 13 [+] Feedback CY29350 Ordering Information Part Number CY29350AXI CY29350AXIT 32-pin TQFP, Pb-free 32-pin TQFP – Tape and Reel, Pb-free Package Type Product Flow Industrial, –40 °C to +85 °C Industrial, –40 °C to 85 °C Ordering Code Definitions CY 29350 AX X T T = Tape and Reel Temperature Range: X = C or I C = Commercial; I = Industrial Package Type: AX = 32-pin TQFP Base Device Part Number Company ID: CY = Cypress Package Drawing and Dimension Figure 4. 32-pin TQFP 7 x 7 x 1.0 mm A3210 51-85063 *C Document Number: 38-07474 Rev. *C Page 10 of 13 [+] Feedback CY29350 Acronyms Acronym CMOS ESD I/O LVCMOS LVTTL PLL TQFP VCO Description complementary metal oxide semiconductor electrostatic discharge Input/Output Low Voltage Complementary Metal Oxide Semiconductor Low Voltage Transistor-Transistor Logic phase-locked loop thin quad flat pack voltage-controlled oscillator Document Conventions Units of Measure Symbol °C Hz kHz MHz µF µA mm mA ms ns  % pF ppm ps kV mV V W degree Celsius Hertz kilo Hertz Mega Hertz micro Farads micro Amperes milli meter milli Amperes milli seconds nano seconds ohms percent pico Farads parts per million pico seconds kilo Volts milli Volts Volts Watts Unit of Measure Document Number: 38-07474 Rev. *C Page 11 of 13 [+] Feedback CY29350 Document History Page Document Title:CY29350 2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Document Number: 38-07474 Rev. ** *A *B ECN No. 128104 245393 2904632 Issue Date 07/07/03 See ECN 04/05/2010 Orig. of Change RGL RGL KVM New Data Sheet Re-worded Select Function Descriptions in table 2. The existing part numbers are replaced with new ones: CY29350AXI and CY29350AXIT with package type cells: [32-pin TQFP, Pb-free] [32-pin TQFP – Tape and Reel, Pb-free]. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated in new template. Description of Change *C 3223621 04/12/2011 BASH Document Number: 38-07474 Rev. *C Page 12 of 13 [+] Feedback CY29350 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2003-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07474 Rev. *C Revised April 12, 2011 Page 13 of 13 Spread Aware is a trademark of Cypress Semiconductor. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback