CY29653AI

CY29653 3.3V 125-MHz 8-Output Zero Delay Buffer Features • Output frequency range: 25 MHz to 125 MHz • Input frequency range (÷4): 35 MHz to 125 MHz • 30 ps typical peak cycle-to-cycle jitter • 30 ps typical out-to-output skew • 3.3V operation • Eight Clock outputs: Drive up to 16 clock lines • One feedback output • LVPECL reference clock input • Phase-locked loop (PLL) bypass mode • Spread Aware™ • Output enable/disable • Pin-compatible with MPC9653 and MPC953 • Industrial temperature range: –40°C to +85°C • 32-pin 1.0-mm TQFP package Description The CY29653 is a low-voltage high-performance 125-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29653 features an LVPECL reference clock input and provides eight outputs plus one feedback output. VCO output divides by four or eight per VCO_SEL setting (see the Function Table). Each LVCMOS-compatible output can drive 50Ω series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:16. The PLL is ensured stable given that the VCO is configured to run between 140 MHz to 500 MHz. This allows a wide range of output frequencies from 25 MHz to 125 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see the Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. When BYPASS# is set LOW, PLL and output dividers are bypassed resulting in a 1:9 LVPECL to LVCMOS high performance fanout buffer. For normal PLL operation both PLL_EN and BYPASS# are set HIGH. • Input frequency range (÷8): 25 MHz to 62.5 MHz Block Diagram Pin Configuration VCO_SEL BYPASS# FB_OUT PLL_EN VDD 27 VSS 32 31 30 29 28 26 PECL_CLK PECL_CLK# FB_IN Phase Detector VCO 200-500MHz LPF ÷2 ÷4 Q(0:6) Q7 AVDD F B _ IN NC NC NC NC AVSS P EC L_C LK 1 2 3 4 5 6 7 8 25 24 23 22 21 20 19 18 17 FB_OUT VSS Q0 C Y 29653 Q1 VDDQ Q2 VSS Q3 VDDQ Q4 VSS 9 10 11 12 13 14 Q6 15 VDDQ BYPASS# PECL_CLK# MR/OE# Q7 PLL_EN Cypress Semiconductor Corporation Document #: 38-07477 Rev. *C • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 13, 2004 VDDQ VSS Q5 MR/OE# 16 VCO_SEL CY29653 Pin Description[1] Pin 8 9 12, 14, 16, 18, 20, 22, 24, 26 28 2 Name PECL_CLK PECL_CLK# Q(7:0) I/O I, PU I, PU O Type LVPECL LVPECL LVCMOS Description LVPECL reference clock input LVPECL reference clock input. Pull-up to VDD/2. Clock output FB_OUT FB_IN O I, PU LVCMOS LVCMOS Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Frequency Table. Output enable/disable input. See Function Table. PLL enable/disable input. See Function Table. PLL and output divider bypass select input. See Function Table. VCO divider select input. See Function Table. 3.3V Power supply for output clocks[2] 3.3V Power supply for PLL[2] 3.3V Power supply for core and inputs[2] Analog Ground Common Ground No connection 10 30 31 32 1 27 7 13, 17, 21, 25, 29 3, 4, 5, 6 MR/OE# PLL_EN BYPASS# VCO_SEL AVDD VDD AVSS VSS NC I, PD I, PU I, PU I, PU Supply Supply Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD Ground Ground 11, 15, 19, 23 VDDQ Frequency Table Feedback Output Divider ÷4 ÷8 VCO Input Clock * 4 Input Clock * 8 Input Frequency Range 35 MHz to 125 MHz 25 MHz to 62.5 MHz Function Table Control VCO_SEL PLL_EN BYPASS# Default 1 1 1 VCO ÷ 1 Bypass mode, PLL disabled. The input clock connects to the output dividers Bypass mode with PLL and output dividers bypassed. The input clock connects to the outputs. Outputs enabled 0 VCO ÷ 2 PLL enabled. The VCO output connects to the output dividers Selects the output dividers 1 MR/OE# 0 Outputs disabled (three-state), VCO running at its minimum frequency Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (