CY29658AI

CY29658 2.5V or 3.3V 200-MHz 10-Output Zero Delay Buffer Features • • • • • • • • • • • • • Output frequency range: 50 MHz to 200 MHz Input frequency range: 50 MHz to 200 MHz 2.5V or 3.3V operation Ten clock outputs: drive up to 20 clock lines One Feedback output LVPECL reference clock input 150-ps max output-output skew Phase-locked loop (PLL) bypass mode Spread Aware™ Output enable/disable Pin-compatible with MPC9658 and MPC958 Industrial temperature range: –40°C to +85°C 32-Pin 1.0mm TQFP package Description The CY29658 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The CY29658 features an LVPECL reference clock input and provides ten outputs plus one feedback output. VCO output divides by two or four per VCO_SEL setting (see Function Table). Each LVCMOS-compatible output can drive 50Ω series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 50 MHz to 200 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Frequency Table). When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. When BYPASS# is set LOW, PLL and output dividers are bypassed resulting in a 1:11 LVPECL to LVCMOS high performance fanout buffer. For normal PLL operation, both PLL_EN and BYPASS# are set HIGH. Block Diagram Pin Configuration VCO_SEL FB_OUT VDDQ VDD 27 VSS 32 31 30 29 28 26 PECL_C LK PEC L_CLK# FB_IN Phase Detector VC O 200-480M LPF VC _SEL O BYPASS# M E# R/O PLL_EN /2 /2 25 FB_O T U Q (0:8) Q 9 AVDD F B _IN BYPASS# P LL_E N M R /O E# P E C L_C LK P E C L_C LK # A V SS 1 2 3 4 5 6 7 8 VSS Q0 Q1 C Y 29658 24 23 22 21 20 19 18 17 Q2 VDDQ Q3 VSS Q4 VDDQ Q5 VSS 9 10 11 12 13 14 Q7 15 VDDQ Q9 Q8 VDDQ VSS Cypress Semiconductor Corporation Document #: 38-07478 Rev. ** • 3901 North First Street • San Jose, CA 95134 VSS • 408-943-2600 Revised May 14, 2003 Q6 16 CY29658 Pin Description[1] Pin 6 7 Name PECL_CLK PECL_CLK# I/O I, PU I, PU O Type LVPECL LVPECL LVCMOS Description LVPECL reference clock input. LVPECL reference clock input. Pull-up to VDD/2. Clock output. 10, 12, 14, Q(9:0) 16, 18, 20, 22, 24, 26, 28 30 2 FB_OUT FB_IN O I, PU LVCMOS LVCMOS Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. PLL enable/disable input. See Table 2. PLL and output divider bypass select input. See Table 2. VCO divider select input. See Table 2. 2.5V or 3.3V power supply for output clocks.[2,3] 2.5V or 3.3V power supply for PLL.[2,3] 2.5V or 3.3V power supply for core and inputs.[2,3] Analog ground. Common ground. 5 4 3 32 11, 15, 19, 23, 31 1 27 8 MR/OE# PLL_EN BYPASS# VCO_SEL VDDQ AVDD VDD AVSS I, PD I, PU I, PU I, PU Supply Supply Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD Ground Ground 9, 13, 17, 21, VSS 25, 29 Table 1. Frequency Table Feedback Output Divider ÷2 ÷4 Table 2. Function Table Control VCO_SEL PLL_EN BYPASS# Default 1 1 1 VCO Input Clock * 2 Input Clock * 4 Input Frequency Range (AVDD = 3.3V) 100 MHz to 200 MHz 50 MHz to 125 MHz Input Frequency Range (AVDD = 2.5V) 100 MHz to 200 MHz 50 MHz to 100 MHz 0 VCO ÷ 1 1 VCO ÷ 2 Bypass mode, PLL disabled. The input PLL enabled. The VCO output connects to the clock connects to the output dividers output dividers Bypass mode with PLL and output dividers bypassed. The input clock connects to the outputs. Outputs enabled Selects the output dividers MR/OE# 0 Outputs disabled (three-state), VCO running at its minimum frequency Notes: 1. PU = Internal pull-up, PD = Internal pull-down. 2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (