CY29774AI

774 CY29774 2.5V or 3.3V, 125-MHz, 14 Output Zero Delay Buffer Features • • • • • • • • • • • • • • Output frequency range: 8.3 MHz to 125 MHz Input frequency range: 4.2 MHz to 62.5 MHz 2.5V or 3.3V operation Split 2.5V/3.3V outputs 14 Clock outputs: Drive up to 28 clock lines 1 Feedback clock output 2 LVCMOS reference clock inputs 150 ps max output-output skew PLL bypass mode Spread Aware™ Output enable/disable Pin compatible with MPC9774 Industrial temperature range: –40°C to +85°C 52-Pin 1.0-mm TQFP package The CY29774 features two reference clock inputs and provides 14 outputs partitioned in 3 banks of 5, 5, and 4 outputs. Bank A and Bank B divide the VCO output by 4 or 8 while Bank C divides by 8 or 12 per SEL(A:C) settings, see Functional Table. These dividers allow output to input ratios of 6:1, 4:1, 3:1, 2:1, 3:2, 4:3, 1:1, and 2:3. Each LVCMOS compatible output can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:28. The PLL is ensured stable given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies from 8.3 MHz to 125 MHz. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider, see Frequency Table. When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply. Description The CY29774 is a low-voltage high-performance 125-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. Block Diagram Pin Configuration V C O _S E L P L L_ E N TC LK _ S EL TC LK 0 T C LK 1 FB _IN VCO_SEL VDDQC QC0 VDDQC QC2 QB0 VDDQB QC1 QC3 VSS VSS VSS NC PLL 20 0 5 00M H z ÷2 ÷4 ÷2 / ÷4 CLK S TO P SELA ÷2 / ÷4 CLK STOP Q A0 Q A1 Q A2 Q A3 Q A4 QB0 QB1 Q B2 QB3 QB4 QC0 QC1 QC2 QC3 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE CLK_STP# SELB SELC PLL_EN SELA TCLK_SEL TCLK0 TCLK1 NC VDD AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB1 VDDQB QB2 VSS QB3 VDDQB QB4 FB_IN VSS FB_OUT VDDFB NC CY29774 S E LB ÷4 / ÷6 CLK STOP S E LC C LK _ S TP # 14 15 16 17 18 19 20 21 22 23 24 25 26 FB_SEL0 AVSS VDDQA QA4 QA3 VSS QA2 FB_SEL1 VDDQA QA1 VSS VDDQA QA0 ÷ 4 / ÷ 6 / ÷ 8 / ÷ 12 F B _O U T F B _S E L(1,0) M R #/O E Cypress Semiconductor Corporation Document #: 38-07479 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised April 28, 2003 CY29774 Pin Description[1] Pin 9 10 16, 18, 21, 23, 25 32, 34, 36, 38, 40 44, 46, 48, 50 29 31 Name TCLK0 TCLK1 QA(4:0) QB(4:0) QC(3:0) FB_OUT FB_IN I/O I, PD I, PU O O O O I, PU Type LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Description LVCMOS/LVTTL reference clock input LVCMOS/LVTTL reference clock input Clock output bank A Clock output bank B Clock output bank C Feedback clock output. Connect to FB_IN for normal operation. Feedback clock input. Connect to FB_OUT for normal operation. This input should be at the same voltage rail as input reference clock. See Table 1. Output enable/disable input. See Table 2. Clock stop enable/disable input. See Table 2. PLL enable/disable input. See Table 2. Reference select input. See Table 2. VCO divider select input. See Table 2. Frequency select input, Bank (A:C). See Table 3. Feedback dividers select input. See Table 4. 2.5V or 3.3V Power supply for bank A output clocks[2,3] 2.5V or 3.3V Power supply for bank B output clocks[2,3] 2.5V or 3.3V Power supply for bank C output clocks[2,3] 2.5V or 3.3V Power supply for feedback output clock[2,3] 2.5V or 3.3V Power supply for PLL[2,3] 2.5V or 3.3V Power supply for core and inputs[2,3] Analog Ground Common Ground 2 3 6 8 52 7, 4, 5 20, 14 17, 22, 26 33, 37, 41 45, 49 28 13 12 15 1, 19, 24, 30, 35, 39, 43, 47, 51 11, 27, 42 MR#/OE CLK_STP# PLL_EN TCLK_SEL VCO_SEL SEL(A:C) FB_SEL(1,0) VDDQA VDDQB VDDQC VDDFB AVDD VDD AVSS VSS I, PU I, PU I, PU I, PD I, PD I, PD I, PD Supply Supply Supply Supply Supply Supply Supply Supply LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS VDD VDD VDD VDD VDD VDD Ground Ground NC No Connection Notes: 1. PU = Internal pull up, PD = Internal pull down 2. A 0.1-µF bypass capacitor should be placed as close as possible to each positive power pin (