CY29940-1

CY29940-1 2.5V or 3.3V, 200-MHz 1:18 Clock Distribution Buffer Features • • • • • • • 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 150 ps max. output-to-output skew 23Ω output impedance Dual or single supply operation: — 3.3V core and 3.3V outputs — 3.3V core and 2.5V outputs — 2.5V core and 2.5V outputs • Pin-compatible with MPC940L, MPC9109 • Available in commercial and industrial temperature ranges • 32-pin TQFP package Description The CY29940-1 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECLor a LVCMOS/LVTTL-compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL-compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940-1 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. Block Diagram Pin Configuration VDDC VDD PECL_CLK PECL_CLK# TCLK TCLK_SEL 0 1 VDDC VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 Q6 Q7 Q8 VDD Q9 Q10 Q11 VSS 18 VSS Q0-Q17 TCLK TCLK_SEL PECL_CLK PECL_CLK# VDD VDDC CY29940-1 VSS 21 20 19 18 17 VDDC Q0 Q1 Q2 Q3 Q4 Q13 Q17 Q16 Q15 Q14 Cypress Semiconductor Corporation Document #: 38-07487 Rev. ** • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised January 28, 2003 VSS Q12 Q5 CY29940-1 Pin Description[1] Pin 5 6 3 Name PECL_CLK PECL_CLK# TCLK VDDC PWR I/O I, PU PECL Input Clock I, PD PECL Input Clock I, PD External Reference/Test Clock Input O Clock Outputs Description 9, 10, 11, 13, Q(17:0) 14, 15, 18, 19, 20, 22, 23, 24, 26, 27, 28, 30, 31, 32 4 8, 16, 29 7, 21 TCLK_SEL VDDC VDD I, PD Clock Select Input. When LOW, PECL clock is selected and when HIGH TCLK is selected. 3.3V or 2.5V Power Supply for Output Clock Buffers 3.3V or 2.5V Power Supply Common Ground 1, 2, 12, 17, 25 VSS Note: 1. PD = Internal Pull-down; PU = Internal Pull-up. Document #: 38-07487 Rev. ** Page 2 of 7 CY29940-1 Absolute Maximum Conditions Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature: ................................ –40°C to +85°C Maximum ESD Protection............................................... 2 kV Maximum Power Supply: ................................................5.5V Maximum Input Current: ............................................±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Electrical Specifications: VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5% Parameter VIL VIH IIL IIH VPP VCMR VOL VOH IDDQ IDD Description Input Low Voltage Input High Voltage Input Low Current[2] 500 VDD = 3.3V VDD = 2.5V IOL = 20 mA, VDDC = 3.3V IOL = 16 mA, VDDC = 2.5V Output High Voltage[4,5,6] Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs @ 150 MHz, CL=10 pF VDD = 3.3V, Outputs @ 200 MHz, CL=10 pF VDD = 2.5V, Outputs @ 150 MHz, CL=10 pF VDD = 2.5V, Outputs @ 200 MHz, CL=10 pF Zout Cin Output Impedance Input Capacitance 18 IOH = –20 mA, VDDC = 3.3V IOH = –16 mA, VDDC = 2.5V 2.4 1.8 5 285 335 200 240 23 4 28 Ω pF 7 mA mA V VDD – 1.4 VDD – 1.0 Input High Current[2] Peak-to-Peak Input Voltage PECL_CLK Common Mode Range[3] PECL_CLK Output Low Voltage[4,5,6] Conditions Min. VSS 2.0 Typ. Max. 0.8 VDD –200 200 1000 VDD – 0.6 VDD – 0.6 0.5 V Unit V V µA µA mV V Notes: 2. Inputs have pull-up/pull-down resistors that effect input current. 3. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. 4. Outputs driving 50Ω transmission lines. 5. See Figure 1 and Figure 2. 6. 50% input duty cycle. Document #: 38-07487 Rev. ** Page 3 of 7 CY29940-1 AC Electrical Specifications (VDD = 3.3V ±5% or 2.5V ±5%, VDDC = 3.3V ±5% or 2.5V ±5%)[7] Parameter Fmax TPD Description Input Frequency PECL_CLK to Q Delay[4,5,10]