CY29946_11

CY29946 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are LVCMOS or LVTTL compatible and can drive 50  series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. The CY29946 is capable of generating 1× and 1/2× signals from a 1× source. These signals are generated and retimed internally to ensure minimal skew between the 1× and 1/2× signals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1× to1/2× outputs. The CY29946 outputs can also be three-stated via MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs. 2.5 V or 3.3 V operation 200-MHz clock support Two LVCMOS-/LVTTL-compatible inputs Ten clock outputs: drive up to 20 clock lines 1× or 1/2× configurable outputs Output three-state control 250-ps max output-to-output skew Pin-compatible with MPC946, MPC9446 Available in commercial and industrial temperature range 32-pin TQFP package Block Diagram TCLK_SEL TCLK0 TCLK1 DSELA /1 R /1 0 1 3 QA0:2 /2 0 3 QB0:2 1 R /2 DSELB /1 0 1 4 QC0:3 R /2 DSELC MR/OE# Cypress Semiconductor Corporation Document #: 38-07286 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 11, 2011 [+] Feedback CY29946 Pin Configuration MR/OE# VSS QA0 VDDC QA1 VSS QA2 VDDC TCLK_SEL VDD TCLK0 TCLK1 DSELA DSELB DSELC VSS 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CY29946 VSS QB0 VDDC QB1 VSS QB2 VDDC VDDC Pin Description[1] Pin 3, 4 26, 28, 30 19, 21, 23 10, 12, 14, 16 5, 6, 7 1 32 Name TCLK(0,1) QA(2:0) QB(2:0) QC(0:3) DSEL(A:C) TCLK_SEL MR/OE# VDDC VDDC VDDC PWR I/O I, PU O O O I, PD I, PD I, PD Clock Outputs Clock Outputs Clock Outputs Divider Select Inputs. When HIGH, selects 2 input divider. When LOW, selects 1 input divider. TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. If more than 1 Bank is being used in /2 Mode, a reset must be performed (MR/OE# Asserted High) after power-up to ensure all internal flip-flops are set to the same state. 2.5 V or 3.3 V Power Supply for Output Clock Buffers 2.5 V or 3.3 V Power Supply Common Ground Description External Reference/Test Clock Input 9, 13, 17, 18, 22, 25, 29 2 8, 11, 15, 20, 24, 27, 31 VDDC VDD VSS Note 1. PD = Internal pull-down. PU = Internal pull-up. Document #: 38-07286 Rev. *G VDDC QC0 VSS QC1 VDDC QC2 VSS QC3 9 10 11 12 13 14 15 16 Page 2 of 9 [+] Feedback CY29946 Absolute Maximum Conditions[2] Maximum Input Voltage Relative to VSS ............. VSS – 0.3 V Maximum Input Voltage Relative to VDD............. VDD + 0.3 V Storage Temperature ................................ –65 C to +150 C Operating Temperature............................... –40 C to +85 C Maximum ESD protection............................................... 2 kV Maximum Power Supply................................................ 5.5 V Maximum Input Current ............................................. ±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD . Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Electrical Specifications VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range Parameter VIL VIH IIL IIH VOL VOH IDDQ IDD Description Input Low Voltage Input High Voltage Input Low Current[3] Voltage[4] IOL = 20 mA IOH = –20 mA, VDD = 3.3 V IOH = –20 mA, VDD = 2.5 V Quiescent Supply Current Dynamic Supply Current VDD = 3.3 V, Outputs @ 100 MHz, CL = 30 pF VDD = 3.3 V, Outputs @ 160 MHz, CL = 30 pF VDD = 2.5 V, Outputs @ 100 MHz, CL = 30 pF VDD = 2.5 V, Outputs @ 160 MHz, CL = 30 pF ZOut Cin Output Impedance Input Capacitance VDD = 3.3 V VDD = 2.5 V Input High Current[3] Output Low Output High Voltage[4] Conditions Min VSS 2.0 – – – 2.5 1.8 – – – – – 12 14 – Typ – – – – – – – 5 130 225 95 160 15 18 4 Max 0.8 VDD –100 100 0.4 – – 7 – – – – 18 22 – pF W mA mA Unit V V µA µA V V Notes 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is not required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. Driving series or parallel terminated 50  (or 50  to VDD/2) transmission lines. Document #: 38-07286 Rev. *G Page 3 of 9 [+] Feedback CY29946 AC Electrical Specifications VDD = VDDC = 3.3 V ± 10% or 2.5 V ± 5%, over the specified temperature range[5] Parameter Fmax Tpd FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew(pp) Tr/Tf Description Input Frequency[6] TTL_CLK To Q Delay[6] Output Duty Cycle [6, 7] Conditions VDD = 3.3 V VDD = 2.5 V Measured at VDD/2 Min – – 5.0 45 2 2 – – 0.10 0.10 Typ – – – – – – 150 2.0 – – Max 200 170 11.5 55 10 10 250 4.5 1.0 1.3 Unit MHz ns % ns ns ps ns ns Output enable time (all outputs) Output disable time (all outputs) Output-to-Output Skew[6, 8] Part-to-Part Skew[9] 0.6 V to 1.8 V, VDD = 2.5 V Output Clocks Rise/Fall Time[8] 0.8 V to 2.0 V, VDD = 3.3 V Notes 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50 transmission lines. 7. 50% input duty cycle. 8. See Figure 1 on page 5. 9. Part-to-Part skew at a given temperature and voltage. Document #: 38-07286 Rev. *G Page 4 of 9 [+] Feedback CY29946 Figure 1. LVCMOS_CLK CY29946 Test Reference for VCC = 3.3 V and VCC = 2.5 V CY29946 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm Zo = 50 ohm RT = 50 ohm VTT VTT Figure 2. LVCMOS Propagation Delay (TPD) Test Reference LVCMOS_CLK VCC VCC /2 GND VCC Q VCC /2 t PD GND Figure 3. Output Duty Cycle (FoutDC) VCC tP T0 VCC /2 G ND DC = tP / T0 x 100% Figure 4. Output-to-Output Skew tsk(0) VCC VCC /2 GND VCC VCC /2 tSK(0) GND Document #: 38-07286 Rev. *G Page 5 of 9 [+] Feedback CY29946 Ordering Information Part Number CY29946AXC CY29946AXCT CY29946AXI CY29946AXIT 32-pin TQFP 32-pin TQFP – Tape and Reel 32-pin TQFP 32-pin TQFP – Tape and Reel Package Type Production Flow Commercial, 0 C to +70 C Commercial, 0 C to +70 C Industrial, –40 C to +85 C Industrial, –40 C to +85 C Ordering Code Definitions CY 29946 A X X T T = Tape and Reel; blank = Tube Temperature Range: X = C or I C = Commercial; I = Industrial Pb-free Package: A = 32-pin TQFP Base part number Company ID: CY = Cypress Package Drawing and Dimensions Figure 5. 32-pin TQFP 7 × 7 × 1.0 mm A3210 51-85063 *C Document #: 38-07286 Rev. *G Page 6 of 9 [+] Feedback CY29946 Acronyms Acronym ESD I/O LVCMOS LVTTL TQFP input/output low voltage complementary metal oxide semiconductor low-voltage transistor-transistor logic thin quad flat pack Document Conventions Description Units of Measure Symbol °C kV MHz µA mA mm mV ns  % pF ps V W degree Celsius kilo Volts Mega Hertz micro Amperes milli Amperes milli meter milli Volts nano seconds ohms percent pico Farad pico seconds Volts Watts electrostatic discharge Unit of Measure Document #: 38-07286 Rev. *G Page 7 of 9 [+] Feedback CY29946 Document History Page Document Title: CY29946, 2.5 V or 3.3 V, 200-MHz, 1:10 Clock Distribution Buffer Document Number: 38-07286 REV. ** *A *B *C *D *E *F *G ECN NO. 111097 116780 122878 130007 131375 221587 2899714 3254185 Issue Date 02/07/02 08/15/02 12/22/02 10/15/03 11/21/03 See ECN 03/26/10 05/11/2011 Orig. of Change BRK HWT RBI RGL RGL RGL CXQ New data sheet Description of Change Added the commercial temperature range in the Ordering Information Added power-up requirements to Maximum Ratings Fixed the block diagram. Fixed the MK/OE# description in the pin description table. Updated document history page (revision *C) to reflect changes that were not listed. Minor Change: Moved up the word Block Diagram in the first page. Added Ordering Code Definitions. Added Acronyms and Units of Measure. Updated in new template. BRIJ/CXQ Removed inactive parts from the ordering table. Updated package diagram Document #: 38-07286 Rev. *G Page 8 of 9 [+] Feedback CY29946 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2002-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07286 Rev. *G Revised May 11, 2011 Page 9 of 9 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback