CY29949AXIT

CY29949 2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer Features ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Description The CY29949 is a low voltage 200 MHz clock distribution buffer with the capability to select either a differential LVPECL or LVCMOS/LVTTL compatible input clocks. These clock sources are used to provide for test clocks and primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 15 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:30. The CY29949 is capable of generating 1X and 1/2X signals from a 1X source. These signals are generated and retimed internally to ensure minimal skew between the 1X and 1/2X signals. SEL(A:D) inputs allow flexibility in selecting the ratio of 1X to1/2X outputs. The CY29949 outputs can also be three-stated via the MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs. 2.5V or 3.3V operation 200-MHz clock support LVPECL or LVCMOS/LVTTL clock input LVCMOS/LVTTL compatible outputs 15 clock outputs: drive up to 30 clock lines 1X and 1/2X configurable outputs Output three-state control 350 ps maximum output-to-output skew Pin compatible with MPC949, MPC9449 Available in Commercial and Industrial temperature range 52-pin TQFP package Logic Block Diagram TCLK_SEL 0 1 0 1 R 1 2 PECL_CLK PECL_CLK# PECL_SEL DSELA 0 1 2 QA(0:1) 1 R 2 0 1 3 QB(0:2) DSELB 1 R 2 0 1 4 QC(0:3) DSELC 1 R2 0 1 6 QD(0:5) DSELD MR/OE# Cypress Semiconductor Corporation Document #: 38-07289 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised October 22, 2008 [+] Feedback CY29949 Pin Configuration Figure 1. Pin Diagram - CY29949 NC VDDC QB2 VSS QB1 VDDC QB0 VSS VSS QA1 VDDC QA0 VSS 52 51 50 49 48 47 46 45 44 43 42 41 40 MR/OE# TCLK_SEL VDD TCLK0 TCLK1 PECL_CLK PECL_CLK# PCLK_SEL DSELA DSELB DSELC DSELD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 NC VSS QC0 VDDC QC1 VSS QC2 VDDC QC3 VSS VSS QD5 NC CY29949 14 15 16 17 18 19 20 21 22 23 24 25 26 NC VDDC QD4 VSS QD3 VDDC QD2 VSS QD1 VDDC QD0 VSS NC Pin Description Pin 6 7 4, 5 49, 51 42, 44, 46 31, 33, 35, 37 9, 10, 11, 12 2 8 1 Name PECL_CLK PECL_CLK# TCLK(0,1) QA(1,0) QB(2:0) QC(3:0) DSEL(A:D) TCLK_SEL PCLK_SEL MR/OE# VDDC VDDC VDDC VDDC PWR I/O[1] I, PD PECL Input Clock I, PU PECL Input Clock I, PU External Reference/Test Clock Input O O O O Clock Outputs Clock Outputs Clock Outputs Clock Outputs Description 16, 18, 20, 22, 24, 28 QD(5:0) I, PD Divider Select Inputs. When HIGH, selects ÷2 input divider. When LOW, selects ÷1 input divider. I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. I, PD PECL Select Input. When HIGH, PECL clock is selected and when LOW TCLK(0,1) is selected I, PD Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. If more than one bank is used in /2 mode, a reset must be performed (MR/OE# asserted high) after power up to ensure that all internal flip-flops are set to the same state. 2.5V or 3.3V Power Supply for Output Clock Buffers 2.5V or 3.3V Power Supply Common Ground 17, 21, 25, 32, 36, 41, 45, 50 3 13, 15, 19, 23, 29, 30, 34, 38, 43, 47, 48, 52 14, 26, 27, 39, 40, VDDC VDD VSS NC Not Connected Note 1. PD = internal pull-down, PU = internal pull-up. Document #: 38-07289 Rev. *E Page 2 of 7 [+] Feedback CY29949 Maximum Ratings[2] Maximum Input Voltage Relative to VSS:............. VSS – 0.3V Maximum Input Voltage Relative to VDD:............. VDD + 0.3V Storage Temperature: ................................ –65°C to + 150°C Operating Temperature:................................ –40°C to +85°C Maximum ESD Protection .............................................. 2 kV Maximum Power Supply:................................................ 5.5V Maximum Input Current: ............................................ ±20 mA This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions must be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: VSS < (Vin or Vout) < VDD Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters (VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range) Parameter VIL Description Input Low Voltage Conditions VDD = 3.3V, PECL_CLK single ended VDD = 2.5V, PECL_CLK single ended All other inputs VIH Input High Voltage VDD = 3.3V, PECL_CLK single ended VDD = 2.5V, PECL_CLK single ended All other inputs IIL IIH VPP VCMR VOL VOH IDDQ IDD Input Low Current[3] Input High Current[3] Peak-to-Peak Input Voltage PECL_CLK Common Mode Range[4] PECL_CLK Output Low Output High Voltage[5] Voltage[5] VDD = 3.3V VDD = 2.5V IOL = 20 mA IOH = –20 mA, VDD = 3.3V IOH = –20 mA, VDD = 2.5V Quiescent Supply Current Dynamic Supply Current VDD = 3.3V, Outputs at 100 MHz, CL = 30 pF VDD = 3.3V, Outputs at 160 MHz, CL = 30 pF VDD = 2.5V, Outputs at 100 MHz, CL = 30 pF VDD = 2.5V, Outputs at 160 MHz, CL = 30 pF Zout Cin Output Impedance Input Capacitance VDD = 3.3V VDD = 2.5V Min 1.49 1.10 VSS 2.135 1.75 2.0 – – 300 VDD – 2.0 VDD – 1.2 – 2.5 1.8 – – – – – 12 14 – 5 200 330 140 235 15 18 4 Typ – – – – – – – – – – – – – Max 1.825 1.45 0.8 2.42 2.0 VDD –100 100 1000 VDD – 0.6 VDD – 0.6 0.4 – – 7 – – – – 18 22 – pF Ω mA mA V V mV V µA V Unit V Notes 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. 5. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Document #: 38-07289 Rev. *E Page 3 of 7 [+] Feedback CY29949 AC Parameters (VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range)[6] Parameter Fmax Tpd Description Input Frequency[7] PECL_CLK to Q Delay[7] TCLK to Q TCLK to Q FoutDC tpZL, tpZH tpLZ, tpHZ Tskew Tskew(pp) Tr/Tf Delay[7] VDD = 2.5V Measured at VDD/2 Delay[7] PECL_CLK to Q Delay[7] Output Duty Cycle[7, 8] Output Enable Time (all outputs) Output Disable Time (all outputs) Output-to-Output Skew[7, 9] PECL_CLK to Q TCLK to Q Output Clocks Rise/Fall Time[9] 0.8V to 2.0V, VDD = 3.3V 0.6V to 1.8V, VDD = 2.5V Part-to-Part Skew[10] Conditions VDD = 3.3V VDD = 2.5V VDD = 3.3V Min – – 4.0 4.2 6.0 6.2 45 2 2 – – – 0.10 0.10 Typ – – – – – – – – – 250 1.5 2.0 – – Max 200 170 8.6 10.5 10.6 10.5 55 10 10 350 2.75 4.0 1.0 1.3 ns % ns ns ps ns ns Unit MHz Figure 2. LVCMOS_CLK CY29949 Test Reference for VCC = 3.3V and VCC = 2.5V CY29949 DUT Pulse Generator Z = 50 ohm Zo = 50 ohm R T = 5 0 ohm Zo = 50 ohm R T = 5 0 ohm VTT VTT Figure 3. PECL_CLK CY29949 Test Reference for VCC = 3.3V and VCC = 2.5V Zo = 50 ohm Differential Pulse Generator Z = 50 ohm CY29949 DUT Zo = 50 ohm Zo = 50 ohm R T = 5 0 ohm R T = 50 ohm VTT VTT Notes 6. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 7. Outputs driving 50Ω transmission lines. 8. 50% input duty cycle. 9. See Figure 2 and Figure 3. 10. Part-to-part skew at a given temperature and voltage. Document #: 38-07289 Rev. *E Page 4 of 7 [+] Feedback CY29949 Figure 4. Propagation Delay (TPD) Test Reference PECL_CLK PECL_CLK VPP VCMR VCC Q VCC /2 tPD GND Figure 5. LVCMOS Propagation Delay (TPD) Test Reference LVCMOS_CLK VCC VCC /2 GND VCC Q VCC /2 tPD GND Figure 6. Output Duty Cycle (FoutDC) VCC tP T0 VCC /2 GND DC = tP / T0 x 100% Figure 7. Output-to-Output Skew tsk(0) VCC VCC /2 GND VCC VCC /2 tSK(0) GND Document #: 38-07289 Rev. *E Page 5 of 7 [+] Feedback CY29949 Ordering Information Part Number CY29949AXI CY29949AXIT CY29949AXC CY29949AXCT Package Type 52-Pin TQFP 52-Pin TQFP - Tape and Reel 52-Pin TQFP 52-Pin TQFP - Tape and Reel Production Flow Industrial, –40°C to +85°C Industrial, –40°C to +85°C Commercial, 0°C to +70°C Commercial, 0°C to +70°C Package Drawing and Dimensions Figure 8. 52-Pin Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A52B 51-85158-** Document #: 38-07289 Rev. *E Page 6 of 7 [+] Feedback CY29949 Document History Page Document Title: CY29949 2.5V or 3.3V 200 MHz 1:15 Clock Distribution Buffer Document Number: 38-07289 Rev. ** *A *B *C *D *E ECN No. 111100 116783 118463 122881 130132 2595534 Submission Date 02/01/02 08/14/02 09/09/02 12/22/02 11/07/03 10/23/08 Orig. of Change BRK HWT HWT RBI RGL New data sheet Description of Change Added commercial temperature range to the Ordering Information table Corrected the package diagram from 52 LQFP to 52 TQFP Added power-up requirements to Maximum Ratings Fixed block diagram and MR/OE# description in the Pin Description table CXQ/PYRS Changed to Pb-Free device code in Ordering Information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2002-2008. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 38-07289 Rev. *E Revised October 22, 2008 Page 7 of 7 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback