CY29973AXI

CY29973 3.3 V 125 MHz Multi-Output Zero Delay Buffer 3.3 V 125 MHz Multi-Output Zero Delay Buffer Features ■ Oscillator or PECL Reference Input ■ Spread Spectrum Compatible ■ Glitch-free Output Clocks Transitioning ■ Output Frequency up to 125 MHz ■ 12 Clock Outputs: Frequency Configurable ■ 350 ps max. Output to Output Skew ■ 3.3 V Power Supply ■ Configurable Output Disable ■ Pin Compatible with MPC973 ■ Two Reference Clock Inputs for Dynamic Toggling ■ Industrial Temperature Range: –40 °C to +85 °C ■ 52-pin TQFP Package Frequency Table [1] VC0_SEL FB_SEL2 FB_SEL1 FB_SEL0 FVC0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x Note 1. x = reference input frequency, 200 MHz < FVCO < 480 MHz. Cypress Semiconductor Corporation Document Number: 38-07291 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 18, 2014 CY29973 Logic Block Diagram PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL D Q TCLK0 TCLK1 Phase Detector 0 1 0 1 VCO Sync Frz LPF TCLK_SEL QA0 QA1 QA2 QA3 FB_IN D Q Sync Frz QB0 QB1 QB2 FB_SEL2 QB3 MR#/OE Power-On Reset D Q Sync Frz D Q Sync Frz D Q Sync Frz FB_OUT D Q Sync Frz SYNC /4, /6, /8, /12 SELA(0,1) 2 SELB(0,1) 2 SELC(0,1) 2 FB_SEL(0,1) 2 QC1 /4, /6, /8, /10 /2, /4, /6, /8 SDATA QC2 QC3 /4, /6, /8, /10 /2 0 1 Sync Pulse SCLK QC0 Data Generator Output Disable Circuitry 12 INV_CLK Document Number: 38-07291 Rev. *F Page 2 of 15 CY29973 Contents Pinouts .............................................................................. 4 Pin Definitions [2] .............................................................. 5 Description ........................................................................ 6 Zero Delay Buffer .............................................................. 6 Glitch-Free Output Frequency Transitions .................... 6 SYNC Output ..................................................................... 7 Power Management .......................................................... 8 Absolute Maximum Conditions ....................................... 9 DC Electrical Specifications ............................................ 9 AC Electrical Specifications .......................................... 10 Ordering Information ...................................................... 11 Ordering Code Definitions ......................................... 11 Document Number: 38-07291 Rev. *F Package Drawing and Dimensions ............................... 12 Acronyms ........................................................................ 13 Document Conventions ................................................. 13 Units of Measure ....................................................... 13 Document History Page ................................................. 14 Sales, Solutions, and Legal Information ...................... 15 Worldwide Sales and Design Support ....................... 15 Products .................................................................... 15 PSoC® Solutions ...................................................... 15 Cypress Developer Community ................................. 15 Technical Support ..................................................... 15 Page 3 of 15 CY29973 Pinouts SELB1 SELB0 SELA1 SELA0 QA3 VDDC QA2 VSS QA1 VDDC QA0 VSS VCO_SEL 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 CY29973 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0 14 15 16 17 18 19 20 21 22 23 24 25 26 FB_SEL1 SYNC VSS QC0 VDDC QC1 SELC0 SELC1 QC2 VDDC QC3 VSS INV_CLK Document Number: 38-07291 Rev. *F Page 4 of 15 CY29973 Pin Definitions [2] Pin Name PWR I/O Type Description 11 PECL_CLK I PU PECL Clock Input. 12 PECL_CLK# I PD PECL Clock Input. 9 TCLK0 I PU External Reference or Test Clock Input. 10 TCLK1 I PU External Reference or Test Clock Input. 44, 46, 48, 50 QA(3:0) VDDC O Clock Outputs. See Divider Table on page 6 for frequency selections. 32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Divider Table on page 6 for frequency selections. 16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Divider Table on page 6 for frequency selections. 29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Frequency Table [1] on page 1. A bypass delay capacitor at this output control Input Reference or Output Banks phase relationships. 25 SYNC VDDC O Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. 42, 43 SELA(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Divider Table on page 6. 40, 41 SELB(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Divider Table on page 6. 19, 20 SELC(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Divider Table on page 6. 5, 26, 27 FB_SEL(2:0) I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Frequency Table [1] on page 1. 52 VCO_SEL I PU VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Frequency Table [1] on page 1. 31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the PLL. 6 PLL_EN I PU PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL is bypassed. 7 REF_SEL I PU Reference Select Input. When HIGH, the PECL inputs are selected. When LOW, TCLK[0:1] are selected. 8 TCLK_SEL I PU TCLK Select Input. When LOW, TCLK0 is selected. When HIGH TCLK1 is selected. 2 MR#/OE I PU Master Reset or Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. 14 INV_CLK I PU Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. 3 SCLK I PU Serial Clock Input. Clocks data at SDATA into the internal register. 4 SDATA I PU Serial Data Input. Input data is clocked to the internal register to enable or disable individual outputs. This provides flexibility in power management. 17, 22, 28, 33,37, 45, 49 VDDC 13 VDD 3.3V Supply for PLL. 1, 15, 24, 30, 35, 39, 47, 51 VSS Common Ground. 3.3V Power Supply for Output Clock Buffers. Note 2. A bypass capacitor (0.1F) must be placed as close as possible to each positive power (