CY29973AXIT

CY29973 3.3V 125-MHz Multi-Output Zero Delay Buffer Features ■ ■ ■ ■ ■ ■ Output Frequency up to 125 MHz 12 Clock Outputs: Frequency Configurable 350 ps max. Output to Output Skew Configurable Output Disable Two Reference Clock Inputs for Dynamic Toggling Oscillator or PECL Reference Input ■ ■ ■ ■ ■ ■ Spread Spectrum Compatible Glitch-free Output Clocks Transitioning 3.3V Power Supply Pin Compatible with MPC973 Industrial Temperature Range: - 40°C to +85°C 52-Pin TQFP Package Table 1. Frequency Table[1] VC0_SEL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FB_SEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FB_SEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FB_SEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 FVC0 8x 12x 16x 20x 16x 24x 32x 40x 4x 6x 8x 10x 8x 12x 16x 20x Note 1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz. Cypress Semiconductor Corporation Document #: 38-07291 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 09, 2008 [+] Feedback CY29973 Logic Block Diagram PECL_CLK PECL_CLK# VCO_SEL PLL_EN REF_SEL DQ TCLK0 TCLK1 TCLK_SEL FB_IN DQ Sync Frz 0 1 Phase Detector LPF VCO 0 1 Sync Frz QA0 QA1 QA2 QA3 QB0 QB1 FB_SEL2 QB2 QB3 MR#/OE Power-On Reset SELA(0,1) SELB(0,1) SELC(0,1) FB_SEL(0,1) SCLK SDATA INV_CLK Output Disable Circuitry 12 2 2 2 2 /4, /6, /8, /10 Sync Pulse Data Generator DQ /2 0 1 DQ DQ /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8 DQ Sync Frz QC0 QC1 Sync Frz Sync Frz Sync Frz QC2 QC3 FB_OUT SYNC Pinouts SELB1 SELB0 SELA1 SELA0 QA3 VDDC QA2 VSS QA1 VDDC QA0 VSS VCO_SEL 52 51 50 49 48 47 46 45 44 43 42 41 40 VSS MR#/OE SCLK SDATA FB_SEL2 PLL_EN REF_SEL TCLK_SEL TCLK0 TCLK1 PECL_CLK PECL_CLK# VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 39 38 37 36 35 34 33 32 31 30 29 28 27 VSS QB0 VDDC QB1 VSS QB2 VDDC QB3 FB_IN VSS FB_OUT VDDC FB_SEL0 CY29973 14 15 16 17 18 19 20 21 22 23 24 25 26 FB_SEL1 SYNC VSS QC0 VDDC QC1 SELC0 SELC1 QC2 VDDC QC3 VSS INV_CLK Document #: 38-07291 Rev. *C Page 2 of 9 [+] Feedback CY29973 Pin Definitions[2] Pin 11 12 9 10 Name PECL_CLK PECL_CLK# TCLK0 TCLK1 VDDC VDDC VDDC VDDC PWR IO I I I I O O O O Type PU PD PU PU PECL Clock Input. PECL Clock Input. External Reference or Test Clock Input. External Reference or Test Clock Input. Clock Outputs. See Table 2 on page 4 for frequency selections. Clock Outputs. See Table 2 on page 4 for frequency selections. Clock Outputs. See Table 2 on page 4 for frequency selections. Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1 on page 1. A bypass delay capacitor at this output control Input Reference or Output Banks phase relationships. Synchronous Pulse Output. This output is used for system synchronization. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. PU PU PU PU PU PU PU PU PU PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2 on page 4. Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2 on page 4. Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2 on page 4. Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 1 on page 1. VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1 on page 1. Feedback Clock Input. Connect to FB_OUT for accessing the PLL. PLL Enable Input. When asserted HIGH, PLL is enabled. When LOW, PLL is bypassed. Reference Select Input. When HIGH, the PECL inputs are selected. When LOW, TCLK[0:1] are selected. TCLK Select Input. When LOW, TCLK0 is selected. When HIGH TCLK1 is selected. Master Reset or Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. Serial Clock Input. Clocks data at SDATA into the internal register. Serial Data Input. Input data is clocked to the internal register to enable or disable individual outputs. This provides flexibility in power management. 3.3V Power Supply for Output Clock Buffers. 3.3V Supply for PLL. Common Ground. Description 44, 46, 48, 50 QA(3:0) 32, 34, 36, 38 QB(3:0) 16, 18, 21, 23 QC(3:0) 29 FB_OUT 25 SYNC VDDC O 42, 43 40, 41 19, 20 5, 26, 27 52 31 6 7 8 2 SELA(1,0) SELB(1,0) SELC(1,0) FB_SEL(2:0) VCO_SEL FB_IN PLL_EN REF_SEL TCLK_SEL MR#/OE I I I I I I I I I I 14 3 4 17, 22, 28, 33,37, 45, 49 13 INV_CLK SCLK SDATA VDDC VDD I I I PU PU PU 1, 15, 24, 30, VSS 35, 39, 47, 51 Note 2. A bypass capacitor (0.1μF) must be placed as close as possible to each positive power (