CY2CC1810SI

COMLINK™ SERIES CY2CC1810 1:10 Clock Fanout Buffer with Output Enable Features Low-voltage operation VDD range from 2.5 to 3.3V 1:10 fanout Drives either a 50-ohm or 75-ohm transmission line Over voltage tolerant input hot swappable Low input capacitance Low output skew Low propagation delay Typical (tpd < 4 ns) High-speed operation > 200 MHz LVTTL-/LVCMOS-compatible input — Output disable to three-state • Industrial versions available • Packages available include: SOIC/SSOP • • • • • • • • • • • Description The Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industries fastest logic and buffers. The Cypress CY2CC1810 fanout buffer features one input and ten three-state outputs. Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. AVCMOS-type outputs dynamically adjust for variable impedance-matching and eliminate the need for seriesdamping resistors; they also reduce noise overall. Block Diagram Q1 OE# Q2 Q3 Q4 Q5 IN Q6 Q7 Q8 Q9 Q 10 OUTPUT (AVCMOS) Pin Configuration VDD GND Q10 VDD Q9 OE# IN GND GND Q8 VDD Q7 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CY2CC1810 GND Q1 VDD Q2 GND Q3 Q4 GND Q5 VDD Q6 GND GND 24 pin SOIC/SSOP Pin Description Pin Number 1,7,8,12,13,17,20,24 3,10,15,22 5 6 2,4,9,11,14,16,18,19,21,23 Pin Name GND VDD OE# IN Q10........Q1 Ground Power Supply Output Enable Input Output Pin Description Power Power LVTTL/LVCMOS LVTTL/LVCMOS AVCMOS Cypress Semiconductor Corporation Document #: 38-07055 Rev. *C • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised December 14, 2002 COMLINK™ SERIES CY2CC1810 Maximum Ratings[1][2] Storage Temperature: ................................–65°C to + 150°C Ambient Temperature:................................... –40°C to +85°C Supply Voltage to Ground Potential VCC .................................................................. –0.5V to 4.6V Input ................................................................. –0.5V to 5.8V Supply Voltage to Ground Potential (Outputs only) ........................................ –0.5V to VDD + 0.5V DC Output Voltage................................. –0.5V to VDD + 0.5V Power Dissipation........................................................ 0.75W DC Parameter @ 3.3V VDD = 3.3V ± 5%, TA= –40°C to +85°C (see Figure 6) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max) VDD = Min., IIN = –18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V 80 –0.7 VIN = 2.7V VIN = 0.5V IOH = –12 mA IOL = 12 mA 2 Min. 2.3 Typ. 3.3 0.2 0.5 5.8 0.8 1 –1 20 –1.2 –50 100 Max. Unit V V V V uA uA uA V mA uA mV DC Parameter @ 2.5V VDD = 2.5V ± 5%, TA= –40°C to +85°C (see Figure 1) Parameter VOH VOL VIH VIL IIH IIL II VIK IOK OOFF VH Description Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input High Current Input Low Current Input High Current Clamp Diode Voltage Continuous Clamp Current Power-down Disable Input Hysteresis Conditions VDD = Min., VIN = VIH or VIL VDD = Min., VIN = VIH or VIL Guaranteed Logic High Level Guaranteed Logic Low Level VDD = Max. VDD = Max. VDD = Max., VIN = VDD(Max.) VDD = Min., IIN = –18 mA VDD = Max., VOUT = GND VDD = GND, VOUT = < 4.5V 80 –0.7 VIN = 2.4V VIN = 0.5V IOH= –7 mA IOH= 12 mA IOL = 12 mA 1.6 Min. 1.8 1.6 0.65 5.0 0.8 1 –1 20 –1.2 –50 100 Typ. Max. Unit V V V V V uA uA uA V mA uA mV Capacitance Symbol CIN COUT Description Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Typ. 2.5 6.5 Max. Unit pF pF Note: 1. Stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. This is intended to be a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. Document #: 38-07055 Rev. *C Page 2 of 8 COMLINK™ SERIES CY2CC1810 Power Supply Characteristics (See Figure 1) Parameter ∆ICC ICCD Description Delta ICC Quiescent Power Supply Current Dynamic Power Supply Current Total Power Supply Current Test Conditions (IDD @ VDD = Max. and VIN = VDD) – (IDD @ VDD = Max. and VIN = VDD – 0.6V) VDD = Max. Input toggling 50% Duty Cycle, Outputs Open VDD = Max. Input toggling 50% Duty Cycle, Outputs Open fL = 40 MHz fL= fMAX OE# = VDD fL=100 MHz OE# = GND Min. Typ. Max. 50 Unit uA mA/ MHz mA 0.63 IC 25 High-frequency Parametrics Parameter DJ Description Jitter, Deterministic Test Conditions 50% duty cycle tW(50–50) The “point to point load circuit” |Output Jitter – Input Jitter| 50% duty cycle tW(50–50) Standard Load Circuit. 50% duty cycle tW(50–50) The “point to point load circuit” Fmax(20) Maximum frequency VDD = 3.3 V Maximum frequency VDD = 2.5 V tW Minimum pulse VDD = 3.3 V Minimum pulse VDD = 2.5 V 20% duty cycle tW(20–80) The “point to point load circuit” VIN = 3.0V/0.0V VOUT = 2.3V/0.4V The “point to point load circuit” VIN = 2.4V/0.0V VOUT = 1.7V/0.7V The “point to point load circuit” VIN = 3.0V/0.0V F = 100 MHz VOUT = 2.0V/0.8V The “point to point load circuit” VIN = 2.4V/0.0V F = 100 MHz VOUT = 1.7V/0.7V See Figure 8 Min. Typ Max 20 Unit ps Fmax Maximum frequency VDD = 3.3V See Figure 6 See Figure 8 See Figure 8 160 200 200 MHz MHz See Figure 3 See Figure 7 2 100 ns See Figure 2 1 AC Switching Characteristics @ 3.3V VDD = 3.3V ± 5%, TA = –40°C to +85°C (See Figure 6) Parameter tPLH tPHL tPHZ tPLZ tR tF tSK(0) tSK(p) tSK(t) tOFF tON Propagation Delay – Low to High Propagation Delay – High to Low Propagation Delay – High to High Z Propagation Delay – Low to High Z Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) See Figure 12 See Figure 9 See Figure 10 Description See Figure 9 Min. 1.5 1.5 Typ. 3 3 4 3 0.8 0.8 0.2 0.2 0.3 4.0 4.0 Max. 3.9 3.9 Unit nS nS nS nS V/nS V/nS nS nS nS nS nS Pulse Skew: Skew between opposite transitions of the same output See Figure 11 (tPHL – tPLH) Package Skew: Skew between outputs of different packages at the See Figure 13 same power supply voltage, temperature and package type. Delay from OE to Driver Off Delay from OE to Driver on Document #: 38-07055 Rev. *C Page 3 of 8 COMLINK™ SERIES CY2CC1810 AC Switching Characteristics @ 2.5V VDD = 2.5V ± 5%, TA = –40°C to +85°C (See Figure 1) Parameter tPLH tPHL tPHZ tPLZ tR tF tSK(0) tSK(p) tSK(t) tOFF tON Propagation Delay – Low to High Propagation Delay – High to Low Propagation Delay – High to High Z Propagation Delay – Low to High Z Output Rise Time Output Fall Time Output Skew: Skew between outputs of the same package (in phase) See Figure 12 Pulse Skew: Skew between opposite transitions of the same output (tPHL – tPLH) Package Skew: Skew between outputs of different packages at the same power supply voltage, temperature and package type. Delay from OE to Driver Off Delay from OE to Driver on See Figure 11 See Figure 13 See Figure 4 See Figure 5 Description See Figure 4 Min. 1.5 1.5 Typ. 3.8 3.8 5 4 0.4 0.6 0.2 0.2 0.3 5.0 5.0 Max. Unit 3.5 3.5 nS nS nS nS V/nS V/nS nS nS nS nS nS Parameter Measurement Information: VDD @ 2.5V[3,5,6] 500 ohm From O utput Under Test C L = 5 0 pF 500 ohm 2x VDD Open V SS Input tPLH Output 1.25 V 1.25 V tPHL 1.25 V 2.5 V 0V VOH 1.25 V VOL 2.5 V VOL (max) Figure 4. Voltage Waveforms–Propagation Delay Times[9] VOH (min) Figure 1. Load Circuit Output Control (low-level enabling) 1.25 V 0V tPLZ 1.25 V VOL + 0.3V tPHZ 1.25V VOH- 0.3V tw(50-50) Input 1.25 V tw(20-80) Input 1.25 V 1.25 V 2.5 V 0V 2.5 V 0V Waveform 2 S1 at GND Waveform 1 S1 at 2 x VDD tPZL Z 2.5 V VOL VOH ~0 V tPZH Z Figure 2. Voltage Waveforms–Pulse Duration From Output Under Test CL = 3 pF 500 ohm Figure 5. Voltage Waveforms– Enable and Disable Times[4,7,8] Table 1. Test tPLH/tPHL tPLZ/tPZL tPHZ/tPZH S1 Open 2 × VDD VSS See Figure 4 See Figure 5 Figure 3. Point-to-Point Load Circuit Notes: 3. CL includes probe and jig capacitance. 4. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. 5. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50Ω, tR < 2.5 nS, tF < 2.5 nS. 6. Outputs are measured one at a time with one transition per measurement. 7. tPLZ and tPHZ are the same as tDIS. 8. tPZL and tPZH are the same as tEN. 9. tPLH and tPHL are the same as tPD. Document #: 38-07055 Rev. *C Page 4 of 8 COMLINK™ SERIES CY2CC1810 Parameter Measurement Information: VDD @ 3.3V [10,12,13] 500 ohm From Output Under Test CL = 50 pF 500 ohm Output 2x VDD Open VSS Input tPLH 1.5 V 1.5 V tPHL 1.5 V 1.5 V 0V VOH 1.5 V VOL Figure 9. Voltage Waveforms– Propagation Delay Times[16] Figure 6. Load Circuit VOH (min) 3.3 V VOL (max) tw(50-50) Input 1.5 V tw(20-80) Input 1.5 V 1.5 V 2.7 V 0V 2.7 V 0V Output Control (low-level enabling) tPZL Waveform 1 S1 at 2 x VDD Z 1.5 V 0V tPLZ 1.5 V VOL + 0.3V tPHZ 1.5V VOH- 0.3V 3V VOL VOH ~0 V tPZH Waveform 2 S1 at GND Z Figure 7. Voltage Waveforms–Pulse Duration From Output Under Test C L = 3 pF 500 ohm Figure 10. Voltage Waveforms– Enable and Disable Times[11,14,15] Table 2. Test S1 Open 2xVDD VSS See Figure 9 See Figure 10 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Figure 8. Point-to-Point Load Circuit 3V 1.5V INPUT tPLH tPHL 0V VOH 1.5V OUTPUT tsk (P) = VOL l tPHL - tPLH l Figure 11. Pulse Skew–tsk(p) Notes: 10. CL includes probe and jig capacitance 11. Waveform 1 is for an output with internal conditions such that the output is LOW, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH, except when disabled by the output control. 12. All input pulses are supplied by generators having the following characteristics: PRR < 10 MHz, Zo = 50Ω, tR < 2.5 nS, tF < 2.5 nS. 13. The outputs are measured one at a time with one transition per measurement. 14. tPLZ and tPHZ are the same as tDIS. 15. tPZL and tPZH are the same as tEN. 16. tPLH and tPHL are the same as tPD. Document #: 38-07055 Rev. *C Page 5 of 8 COMLINK™ SERIES CY2CC1810 3V 1.5V INPUT tPLH1 tPHL1 0V VOH 1.5V OUTPUT 1 tsk (O) tsk (O) VOL VOH 1.5V OUTPUT 2 VOL tPLH 2 tPLH 2 tsk (P) = l tPLH 2 - t PLH1 l o r tPHL2 - t PH L1 l 3V 1.5V Figure 12. Output Skew–tsk(0) INPUT tPLH1 tPHL1 0V VOH 1.5V PACKAGE 1 OUTPUT tsk(t) tsk(t) VOL VOH 1.5V PACKAGE 2 OUTPUT VOL tPLH 2 tPLH 2 tsk(t) = l tPLH2 - tPLH1 l or tPHL2 - tPHL1 l Figure 13. Package Skew - tsk(t) Ordering Information Part Number CY2CC1810SI CY2CC1810SIT CY2CC1810OI CY2CC1810OIT CY2CC1810SC CY2CC1810SCT CY2CC1810OC CY2CC1810OCT Package Type 24-pin SOIC 24-pin SOIC–Tape and Reel 24-pin SSOP 24-pin SSOP–Tape and Reel 24-pin SOIC 24-pin SOIC–Tape and Reel 24-pin SSOP 24-pin SSOP–Tape and Reel Product Flow Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Industrial, –40° to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Document #: 38-07055 Rev. *C Page 6 of 8 COMLINK™ SERIES CY2CC1810 Package Drawing and Dimensions 24-lead (300-mil) Molded SOIC S13 51-85025-A 24-lead (5.3-mm) Shrunk Small Outline Package O24 51-85078-** All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07055 Rev. *C Page 7 of 8 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. COMLINK™ SERIES CY2CC1810 Document History Page Document Title: CY2CC1810 1:10 Clock Fanout Buffer with Output Enable Document #: 38-07055 Orig. of REV. ECN NO. Issue Date Change Description of Change ** 107080 06/07/01 IKA Convert from IMI to Cypress format *A 114316 05/08/02 TSM ∆ IDD validation *B 119147 10/07/02 RGL Added 5.8 as the Max. value for VIH in the DC Parameters @3.3V table. Changed the Max. value of the VIH from 5.8 to 5.0 in the DC Parameters @2.5V table. *C 122742 12/14/02 RBI Added power up requirements to maximum ratings information. Document #: 38-07055 Rev. *C Page 8 of 8